Clock Multiplexer Low-Phase Switching to Prevent Glitches
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Solution Overview
Problem
Existing clock switching circuits in digital chipsets, such as those used in WCDMA handsets, often generate glitches or metastability issues when switching between asynchronous clock sources, which can lead to system failures and inefficiencies.
Innovation Solution
A novel glitch-free clock signal multiplexer circuit that maintains a low phase output level during switching from one clock input to another, ensuring seamless phase alignment and minimizing the likelihood of metastability, by using a method that determines low phase input levels and forces the output to follow the new clock signal after switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional clock multiplexer circuit is used to switch between asynchronous clock sources, then clock switching functionality is achieved, but glitches and metastability issues occur during switching
Solution Approach 1:
The patent applies preliminary action by asserting the second multiplexer output to a predetermined logic level (logic zero) before the switching operation occurs. This pre-positioning of the output ensures that when the switch happens, the output is already in a safe state, preventing glitches and metastability. The control logic prepares the output in advance by forcing it to logic zero during the transition window, so that no matter when the actual clock source switching occurs, the output remains stable.
2Speed
If clock switching is performed without output stabilization, then switching speed is maintained, but output glitches occur
Solution Approach 1:
The patent introduces an intermediary control mechanism that mediates between the fast switching requirement and glitch prevention. The control logic acts as an intermediary by monitoring the switching state and asserting the second multiplexer output to logic zero during the transition. This intermediary action occurs in parallel with the switching operation, so it does not slow down the switching speed while effectively eliminating glitches by controlling the output state during the critical transition window.
3Adaptability or versatility
If multiple asynchronous clocks are used to feed multiple subsystems, then system functionality is improved, but clock switching complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the output parameter (logic level) of the second multiplexer during the switching transition. Instead of changing the physical structure or adding complex control mechanisms, the solution changes the logic state parameter of the output to logic zero during switching. This simple parameter change approach maintains the ability to support multiple asynchronous clocks while avoiding increased circuit complexity.
Data Source
AI summary
Techniques for the design and use of a digital signal processor, including for processing transmissions in a communications system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output. For a limited period of time, a low phase output level is forced. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.