Clock Multiplexer Power-Domain Isolation for Reduced Jitter
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Solution Overview
Problem
Current clock networks suffer from crosstalk and power supply noise when multiplexing signals, leading to increased jitter and potential bit errors due to the close proximity of PLL/DLL devices, which degrades the timing and reliability of electronic systems.
Innovation Solution
A multiplexer circuit with logic gates arranged in separate power domains, where only one active signal is supplied to each logic gate, eliminating crosstalk and power supply noise by using static control signals to deactivate one of the signals, thereby reducing jitter and improving timing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PLL/DLL devices are placed in close proximity for signal multiplexing, then device integration and signal selection capability are improved, but crosstalk and power supply noise increase leading to higher jitter
Solution Approach 1:
The patent divides the clock network into separate power domains, isolating multiple PLL/DLL devices into distinct electrical zones. Each power domain is independently regulated, preventing noise propagation between adjacent devices while maintaining their multiplexing functionality. This segmentation resolves the contradiction by enabling close proximity placement without suffering from crosstalk and power supply noise.
Solution Approach 2:
The patent introduces separate power domains as intermediary zones between multiple PLL/DLL devices. These power domains act as electrical buffers that isolate noise sources while allowing controlled signal distribution. The power domain structure serves as a mediator that enables device integration while filtering out harmful crosstalk and power supply noise.
2Reliability
If clock signals are distributed through a clock network, then system components receive synchronized timing, but timing delays and skew occur causing jitter and bit errors
Solution Approach 1:
The patent segments the clock distribution network into isolated power domains, where each domain maintains independent voltage regulation and timing control. This segmentation prevents noise-induced timing variations from propagating across the entire system, thereby reducing jitter while maintaining synchronization accuracy across distributed components.
Solution Approach 2:
The patent employs separate power domains with independent voltage regulation to change the electrical parameters of each clock signal path. By controlling power delivery independently in each domain, the system compensates for timing delays and skew through parameter adjustment, reducing jitter and preventing bit errors while maintaining overall synchronization.
Data Source
AI summary
An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.