Clock Multiplexer Layout for Low-Jitter Signal Switching
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Solution Overview
Problem
Current clock networks suffer from crosstalk and power supply noise when multiplexing signals, leading to increased jitter and potential bit errors due to the close proximity of components and shared power buses, which degrades the timing and reliability of electronic systems.
Innovation Solution
A multiplexer circuit design utilizing separate logic gates and power domains to isolate signal inputs, with each logic gate receiving only one active signal, eliminating crosstalk and power supply noise by using static control signals and distributing gates across distinct power supply islands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock signals are multiplexed through a single logic gate, then signal routing flexibility is improved, but crosstalk and power supply noise increase leading to higher jitter
Solution Approach 1:
The multiplexer is divided into multiple independent logic gates, each handling a single clock signal. This segmentation isolates the signals physically and electrically, preventing crosstalk and power supply noise between channels while maintaining routing flexibility through selective activation of individual gates.
Solution Approach 2:
Each logic gate is assigned a dedicated power supply island with localized decoupling capacitance, providing tailored power isolation for each signal path. This local quality enhancement ensures that noise from one channel does not affect others, maintaining timing accuracy while allowing flexible signal routing.
2Area of stationary object
If logic gates are placed in close proximity to reduce area, then device area is reduced, but crosstalk between signals increases
Solution Approach 1:
Static control signals act as intermediaries that activate only one logic gate at a time. This ensures that even when gates are placed in close proximity to minimize area, only one gate is active per clock phase, eliminating crosstalk between active signal paths while maintaining compact layout.
Solution Approach 2:
The multiplexer operates by periodically activating different logic gates in sequence, with each gate handling a specific clock phase. This periodic activation pattern ensures that gates are never simultaneously active, preventing crosstalk even in compact arrangements where gates must be closely spaced.
3Device complexity
If shared power buses are used to reduce power distribution complexity, then power distribution complexity is reduced, but power supply noise increases
Solution Approach 1:
The power distribution network is segmented into separate power supply islands, with each logic gate connected to its own dedicated power bus. This segmentation eliminates shared power bus noise while keeping the overall power distribution manageable through modular organization of the islands.
Solution Approach 2:
Each power supply island is designed to maintain equipotential conditions locally through adequate decoupling capacitance, ensuring stable power delivery to each logic gate. This local equipotentiality compensates for the increased complexity of multiple power buses by providing noise-free power delivery.
Data Source
AI summary
A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply noise injection may be eliminated by: (i) separating the multiplexing function into three separate logic gates and (ii) allowing only one switching input per logic gate. In some cases, jitter may be further reduced by distributing the logic gates across three distinct power domains. In other words, the logic gate inputs may be further isolated by gating each signal in its own power domain. In addition, the multiplexer circuit provides built in delay matching by utilizing three substantially identical logic gates.