Low-Frequency Clock Multiplexing for Backplane Interface Reduction
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Solution Overview
Problem
As the number of network interface cards increases in telecommunication systems, the number of clock signals that need to be passed to master and slave controllers also increases, leading to a complex backplane design due to the high number of interface connections required for synchronization, necessitating a method to reduce the interface count for low frequency clock transmission.
Innovation Solution
A method and system for multiplexing low frequency clocks using CLKMUX logic and CLKDEMUX logic, with Mux and Demux selection logic, jitter attenuator, and CLOCK SINK, to reduce the interface count by multiplexing and de-multiplexing clocks, filtering jitter, and distributing system clocks and frames, utilizing interfaces such as backplane connectors, PCB traces, and cables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of network interface cards increases, then the processing capability of the telecommunication system is improved, but the number of clock signals that need to be passed to controllers increases, leading to increased backplane interface connections and design complexity
Solution Approach 1:
Multiple individual clock signals from different network interface cards are merged into a single multiplexed clock signal. The CLKMUX logic combines multiple low-frequency clock inputs (CLK1, CLK2, CLK3, CLK4) into one multiplexed clock output that is transmitted through a single backplane interface to the controller, thereby reducing the number of interface connections required
Solution Approach 2:
A single backplane interface is designed to handle multiple clock signals through time-division multiplexing. The interface becomes universal by carrying different clock signals at different time slots, allowing one interface to perform the function of multiple interfaces would otherwise be needed
2Adaptability or versatility
If multiple clock signals are transmitted separately, then each clock signal can be independently managed, but the interface count increases significantly making the controller and backplane design complex
Solution Approach 1:
The clock signals are transmitted in periodic time slots through the multiplexing system. Each clock signal is assigned a specific time slot in a repeating cycle, allowing periodic transmission of multiple clock signals through a single interface while maintaining independent management of each clock source
Solution Approach 2:
The CLKMUX and CLKDEMUX logic circuits act as intermediary devices that enable efficient clock signal transmission. These intermediaries manage the conversion between multiple separate clock signals and a single multiplexed signal, reducing interface requirements while preserving clock independence
Data Source
AI summary
Embodiments of the present disclosure relate to a method and system for multiplexing the low frequency signals from at least one clock transmitter to at least one clock receiver to reduce interface count. The low frequency signals are multiplexed in a CLKMUX logic using selection signals. The selection signals are generated using system frame and system clocks. The multiplexed clock is received by the CLKDEMUX logic through an interface. The interface can be backplane connectors, PCB traces and cables. The CLKDEMUX logic de-multiplexes the received clock and transmits to the SELECT LOGIC for selecting at least one low frequency clock. The SELECT LOGIC selects at least one low frequency clock based on the signals from a processor. The jitter attenuator filters jitter in the low frequency clock and the CLOCK SINK distributes system clocks to rest of system elements.