Clock Multiplexing Circuit for CML-to-CMOS Clock Distribution
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Solution Overview
Problem
Semiconductor apparatuses face challenges with increased circuit area, power consumption, and reduced signal processing efficiency due to the need for processing external clock signals for input/output terminals, necessitating a more efficient clock distribution system.
Innovation Solution
A clock multiplexing circuit that converts and buffers clock signals based on mode control signals, allowing for CMOS level-signals in high-speed mode and buffering in low-power mode, reducing the number of transmission lines and improving signal reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If external clock signals are processed for input/output terminals, then signal processing capability is improved, but circuit area increases
Solution Approach 1:
The clock multiplexing circuit is designed to perform multiple functions: it can multiplex multiple clock signals into a single output line, and it can also demultiplex clock signals to different destinations. This multi-functionality allows the same circuit structure to handle both clock distribution and signal processing tasks, reducing the need for separate dedicated circuits and thereby reducing overall circuit area while maintaining signal processing capability.
Solution Approach 2:
The patent combines the clock distribution function with the signal processing function into a single integrated circuit structure. By merging these functions, the patent eliminates redundant circuit elements that would exist if separate circuits were used for each function, thus reducing circuit area while preserving the ability to process signals for input/output terminals.
2Productivity
If external clock signals are processed for input/output terminals, then signal processing capability is improved, but power consumption increases
Solution Approach 1:
The clock multiplexing circuit operates by selectively enabling different clock signal paths based on control signals. This periodic switching between different operational modes allows the circuit to process signals only when necessary, rather than continuously operating all signal processing paths, thereby reducing overall power consumption while maintaining signal processing capability when needed.
Solution Approach 2:
The circuit employs dynamic control through enable signals that activate specific signal processing paths based on operational requirements. This dynamic operation allows the circuit to adapt its power consumption to the actual processing needs, consuming power only for the specific clock signal paths that are currently active, thus reducing overall power usage while preserving signal processing capability.
3Productivity
If multiple clock signals are distributed to input/output terminals, then signal processing efficiency is reduced, but clock distribution capability is improved
Solution Approach 1:
The patent segments the clock distribution into multiple phases or paths that can be independently controlled. By dividing the overall clock distribution function into segmented paths with individual enable signals, the circuit can activate only the specific segments needed for current operation, improving signal processing efficiency by avoiding unnecessary signal routing while maintaining the capability to distribute to multiple terminals when required.
Solution Approach 2:
The clock multiplexing circuit acts as an intermediary between the multiple clock signal sources and the input/output terminals. It introduces control logic that mediates which clock signals are actually distributed to which terminals based on operational mode, thereby improving processing efficiency by filtering out unnecessary signal distributions while preserving the adaptability to distribute multiple signals when needed.
Data Source
AI summary
A clock multiplexing circuit includes: a mode control unit configured to generate first enable signals and second enable signals in response to mode control signals; a first multiplexing unit configured to convert first input signals having a current mode logic (CML) level into complementary metal-oxide semiconductor (CMOS) level-signals in response to activation of the first enable signals, and to output the CMOS level-signals; and a second multiplexing unit configured to buffer and output second input signals having the CMOS level in response to the first enable signals and the second enable signals.