Internal Clock Multiplier Using Voltage-Controlled Delay Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing PLL circuits using ring oscillators face limitations in generating high-frequency internal clock signals due to increased circuit scale and power consumption, especially when trying to reduce operating voltage and transistor threshold voltage to minimize power consumption and jitter.
Innovation Solution
A semiconductor device incorporating a multiplier oscillator with a series of delay circuits, a regulator circuit, and a synthesizing circuit to generate an internal clock signal with a higher frequency by controlling the operating voltage and synthesizing clock signals, allowing for higher frequency operation without the need for a ring oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the oscillation frequency of the ring oscillator is increased to generate higher frequency internal clock signals, then the frequency of the internal clock signal is improved, but the circuit scale increases due to the need for boosted potential and additional correction operations
Solution Approach 1:
The patent changes the operating voltage parameter dynamically by introducing a regulator circuit that adjusts the voltage supplied to delay circuits based on phase detection results. This allows frequency multiplication without requiring permanently high voltage circuits, thus avoiding increased circuit scale while achieving higher internal clock frequencies
Solution Approach 2:
The patent implements a feedback mechanism where the phase relationship between input and output clock signals is detected and used to control the operating voltage of delay circuits. This feedback loop enables automatic frequency correction and stabilization, eliminating the need for additional correction circuits that would increase device complexity
2Use of energy by moving object
If the operating voltage is lowered to reduce power consumption and jitter, then power consumption is improved, but the delay amount of each stage increases making it difficult to increase oscillation frequency
Solution Approach 1:
The patent makes the operating voltage dynamic rather than static by introducing a regulator circuit that adjusts voltage levels in real-time based on phase detection. This allows the system to operate at low voltage for power efficiency while dynamically boosting voltage only when and where needed to maintain high frequency performance
Solution Approach 2:
The patent applies different voltage levels to different parts of the circuit - delay circuits receive regulated voltage optimized for their specific phase requirements, while other parts of the system can operate at lower voltages. This localized voltage optimization allows frequency multiplication without proportionally increasing power consumption across the entire device
3Loss of energy
If the transistor threshold voltage is increased to reduce off-leakage current, then power consumption is improved, but the delay amount of each stage increases making it difficult to increase oscillation frequency
Solution Approach 1:
The patent compensates for the increased delay caused by high threshold voltage transistors by dynamically adjusting the operating voltage parameter. The regulator circuit increases voltage to delay circuits when phase detection indicates frequency multiplication is needed, thereby overcoming the speed limitation imposed by high-threshold transistors while maintaining their low leakage benefits
4Measurement precision
If constant frequency correction operations are performed to reduce phase difference, then phase accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements an intelligent feedback mechanism where phase detection results directly control voltage regulation. Correction operations are performed only when phase differences are detected, rather than continuously. This event-driven feedback approach maintains high phase accuracy while minimizing power consumption by activating correction only when necessary
Solution Approach 2:
The patent transforms continuous correction operations into periodic actions triggered by phase detection events. The regulator circuit adjusts voltage in discrete steps based on detected phase relationships, rather than continuously. This periodic correction approach reduces power consumption while maintaining adequate phase accuracy for frequency multiplication
Data Source
AI summary
Disclosed herein is a device that includes: a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, and a control circuit. The delay circuits are coupled in series with the input node of a leading delay circuit receiving a first clock signal and the output node of a last delay circuit producing a second clock signal. The control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines. The first power nodes of the delay circuits are connected in common to the first power line, and the second power nodes the delay circuits are connected in common to the second power line.