Clock Multiplier for Dual Clock Transmission in Semiconductor Systems
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Solution Overview
Problem
The development of semiconductor interface circuits lags behind the increasing frequencies of clock signals, limiting the operating speed of semiconductor apparatuses.
Innovation Solution
A semiconductor system that includes a clock multiplier capable of generating a high-frequency read data strobe signal from two system clock signals with a lower frequency, allowing for faster data transmission by synchronizing data transmission with the high-frequency strobe signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of clock signals is increased to achieve higher operating speeds, then the data transmission speed is improved, but the interface circuits cannot keep up with the increasing speed due to semiconductor processing limitations
Solution Approach 1:
The patent divides the clock signal frequency multiplication into separate stages using multiple clock multipliers. Instead of using a single interface circuit to handle the entire frequency conversion, the system segments the frequency multiplication task across multiple components, allowing each to operate within their processing capabilities while achieving overall high-speed data transmission.
Solution Approach 2:
The patent introduces clock multipliers as intermediary components between the system clock and the data transmission interface. These intermediaries generate intermediate clock signals at multiplied frequencies, bridging the gap between the limited interface circuit speed and the desired high-speed data transmission, thereby enabling faster operation without overloading the interface circuits.
2Speed
If a single clock signal is used for data transmission, then the system is simple to implement, but the data transmission speed is limited by the clock frequency
Solution Approach 1:
The patent employs multiple clock signals with different phases (e.g., 0°, 90°, 180°, 270°) to enable multi-phase data transmission. This periodic action with phase shifts allows data to be transmitted during multiple clock cycles per data unit, effectively multiplying the data transmission rate without requiring a single ultra-high-frequency clock that would overwhelm the interface circuits.
Solution Approach 2:
Instead of increasing only the frequency dimension of a single clock signal, the patent adds a phase dimension by introducing multiple clock signals with different phase offsets. This dimensional expansion allows the system to achieve higher effective transmission speeds by utilizing phase diversity, thereby transmitting more data per unit time without proportionally increasing the base clock frequency and associated interface circuit complexity.
Data Source
AI summary
A semiconductor system may include a first semiconductor apparatus, and a second semiconductor apparatus. The first semiconductor apparatus may be configured to transmit a first system clock signal and a second system clock signal having a first frequency, and transmit a data strobe signal having a second frequency. The second semiconductor apparatus may include a clock multiplier configured to generate a read data strobe signal having the second frequency, based on the first and second system clock signals.