Clock Multiplier Dynamic Lock-Range Tuning for Fast Re-Lock
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Solution Overview
Problem
Conventional phase-locked loop (PLL) multipliers incur significant latency during frequency changes, while injection-locked oscillators offer fast lock times but with limited frequency agility due to their narrow input frequency range, hindering efficient power conservation in frequency-agile systems.
Innovation Solution
A frequency-agile, fast-locking clock multiplier unit that compares a variable-frequency input clock with a self-generated reference clock to rapidly lock a wide-range oscillator to a frequency multiple of the input clock, utilizing spectrally staggered component oscillators and pipelining frequency comparison and injection locking operations to minimize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional phase-locked loop (PLL) multipliers are used, then a broad input frequency range is achieved, but long re-lock times and latency are incurred following frequency changes
Solution Approach 1:
The patent divides the frequency multiplication function into two separate segments: an injection-locked oscillator for fast frequency switching and a phase-locked loop for broad frequency range coverage. By segmenting the system, each component can be optimized for its specific function, achieving both fast lock time and wide frequency range simultaneously
Solution Approach 2:
The patent merges the injection-locked oscillator and phase-locked loop into a unified clock multiplier system. The injection-locked oscillator provides fast frequency transitions while the PLL ensures broad input frequency acceptance, combining the advantages of both architectures to resolve the contradiction between speed and range
2Loss of time
If injection-locked oscillators are used, then fast lock times are achieved, but narrow input frequency range and limited frequency agility are incurred
Solution Approach 1:
The phase-locked loop serves as an intermediary between the injection-locked oscillator and the input clock source. It broadens the effective input frequency range by accepting a wider variety of input frequencies and conditioning them before they reach the injection-locked oscillator, enabling fast locking across a broader frequency spectrum
Solution Approach 2:
The system dynamically switches between injection-locked and PLL modes depending on the operating conditions. During frequency transitions, the injection-locked mode provides fast response, while during steady-state operation across the broad frequency range, the PLL maintains stability and wideband acceptance
Data Source
AI summary
A variable-frequency input clock signal and a reference clock signal are compared during a frequency-compare interval to generate a value that indicates a ratio of their frequencies. The frequency-ratio value is then applied to configure a wide-range frequency-locking oscillator for operation with a narrowed input frequency range. Because the narrowed input frequency range is targeted to the input clock frequency, the wide-range oscillator is able to rapidly lock to a frequency multiple of the input clock frequency. Because the frequency-compare interval is also brief, an extremely fast-locking, clock-multiplying operation may be effected over a relatively wide range of input clock frequencies.