Clock Multiplier Circuit for Low-Jitter Arbitrary Frequency Division
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Solution Overview
Problem
Existing clock generation methods for integrated circuits face challenges in generating a low jitter clock with non-integer divide ratios relative to a high-frequency clock, leading to adverse effects on system performance.
Innovation Solution
The proposed solution involves using a clock divider to apply an integer divide ratio to a high-frequency clock and then employing a variable skew control block to introduce a delay, allowing the clock to achieve non-integer divide ratios without jitter alternation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a clock divider alternates between two integer divide ratios to achieve a non-integer divide ratio, then the desired non-integer frequency division is achieved, but output jitter increases significantly
Solution Approach 1:
The patent applies dynamics by making the divide ratio variable rather than fixed. The clock divider dynamically switches between different integer divide ratios (e.g., 4 and 5) based on a control signal, allowing the system to achieve non-integer average divide ratios (e.g., 4.5) while maintaining low jitter through controlled alternation synchronized to the reference clock edges.
Solution Approach 2:
The patent implements periodic action by alternating between two integer divide ratios in a regular, periodic manner. The clock divider switches between divide ratios at specific intervals synchronized to the reference clock, creating a periodic pattern that achieves the desired non-integer average frequency while maintaining timing precision and minimizing jitter.
2Ease of manufacture
If a single integer divide ratio is used in the clock divider, then the circuit design is simplified, but the ability to generate arbitrary non-integer output frequencies is lost
Solution Approach 1:
The patent achieves universality by designing a clock divider that can perform multiple functions: it can operate with a single integer divide ratio for simple applications, or switch between multiple integer divide ratios for complex applications requiring non-integer frequencies. This multi-functional design allows the same circuit to serve both simplified and flexible operation modes.
Solution Approach 2:
The patent applies dynamics by making the divide ratio variable rather than fixed. The clock divider dynamically switches between different integer divide ratios (e.g., 4 and 5) based on a control signal, allowing the system to achieve non-integer average divide ratios (e.g., 4.5) while maintaining timing precision and minimizing jitter through controlled alternation.
3Adaptability or versatility
If the high-frequency clock frequency is constrained to be an integer multiple of the desired output clock frequency, then integer divide ratios can be used, but the range of achievable output frequencies is limited
Solution Approach 1:
The patent applies parameter changes by allowing the divide ratio parameter to vary between different integer values. Instead of being fixed to a single integer divide ratio, the system changes the divide ratio parameter dynamically based on control signals, enabling the generation of a broader range of output frequencies including non-integer multiples of the reference clock.
Solution Approach 2:
The patent implements dynamics by making the divide ratio adjustable and switchable. The clock divider can be configured to use different integer divide ratios depending on the desired output frequency, allowing the system to adapt to various frequency requirements without being constrained to a fixed integer multiple relationship between the high-frequency clock and output clock.
Data Source
AI summary
A circuit and method are described for generating a low jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing the high-frequency clock by the reference clock and phase locking the output clock to the high-frequency clock. Non-integer divide ratios can be achieved by dividing the high-frequency clock by the nearest integer, rounded down, and then delaying the resultant output clock by the modulus of the division. The delay can then be rotated across to create a clock with a non-integer divide ratio relative to the high-frequency clock. By doing so, a high-frequency clock may be used that is not constrained by having a frequency that is an integer multiple of each desired component-specific output clock signal.