Multi-Stage Clock Multiplier for Low-Noise, Low-Power Generation
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in reducing power consumption and noise in clock signal generation, particularly when increasing the frequency of input clock signals, which often requires large area occupation and high power consumption.
Innovation Solution
A clock generating circuit is designed with a first and second frequency multiplier, including pulse width control circuits, delay circuits, and exclusive OR gates to generate clock signals with higher frequencies while maintaining a 50% duty cycle, thereby reducing noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the frequency of the input clock signal is increased to reduce noise of the generated reference clock signal, then noise is reduced, but the circuit occupies a large area and consumes much power
Solution Approach 1:
The frequency multiplication process is divided into multiple stages: a first frequency multiplier generates an intermediate frequency signal from the input clock signal, and a second frequency multiplier generates the final high-frequency signal from the intermediate signal. This segmentation allows each stage to operate at lower frequencies than a single-stage multiplier would require, reducing power consumption while achieving the desired high output frequency for low noise performance
Solution Approach 2:
An intermediate frequency signal is introduced as a mediator between the low-frequency input clock signal and the high-frequency output signal. The first frequency multiplier generates this intermediate signal, which then serves as the input to the second frequency multiplier. This intermediary approach enables progressive frequency multiplication with reduced power requirements compared to direct high-frequency generation
2Object-affected harmful factors
If the frequency of the input clock signal is increased to reduce noise of the generated reference clock signal, then noise is reduced, but the circuit occupies a large area
Solution Approach 1:
The frequency multiplication function is segmented into two separate multiplier circuits operating in sequence. Each multiplier handles a smaller frequency multiplication ratio, allowing for more compact circuit design compared to a single multiplier handling the entire frequency ratio. This segmentation reduces the total circuit area while enabling high output frequencies for low noise performance
3Adaptability or versatility
If a clock generating circuit is used to generate clock signals with different periods, then operational flexibility is improved, but device complexity increases
Solution Approach 1:
The clock generating circuit is designed with multiple frequency multipliers that can be configured to generate different output frequencies. The same basic circuit architecture serves multiple frequency generation needs, providing operational flexibility for different clock signal requirements without proportionally increasing complexity. The circuit can generate various clock signals with different periods to support diverse operational modes
Data Source
AI summary
A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.