Clock Multiplier and Phase Converter for High-Speed DUT Testing
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Solution Overview
Problem
Small and medium-sized enterprises face economic burdens in testing high-speed semiconductor devices due to the need for expensive high-speed test apparatuses, and existing methods require additional pattern generators and larger apparatuses to accommodate higher operating frequencies.
Innovation Solution
A test apparatus with a clock source, clock multiplier, phase converter, and test pattern comparator that generates and shifts clocks to match the operating frequency of high-speed devices, allowing for sequential data collection and pattern application without multiple pattern generators, reducing apparatus size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed test apparatus is used to test high-speed semiconductor devices, then the test speed and performance match the DUT operating frequency, but the apparatus cost and complexity increase significantly
Solution Approach 1:
The patent divides the high-speed test operation into multiple sequential low-speed operations using multiple pattern generators. Each pattern generator operates at a lower frequency but multiple units work in parallel to achieve the overall high-speed test capability without requiring a single high-frequency apparatus
Solution Approach 2:
The patent combines multiple pattern generators and their output through a multiplexer to create a unified test interface that can handle high-speed DUT testing. The merged system achieves high-speed performance through coordinated operation of multiple lower-speed components
2Productivity
If the test apparatus operating frequency is increased to match DUT frequency, then testing capability improves, but the apparatus becomes economically burdensome for small and medium-sized enterprises
Solution Approach 1:
The patent uses multiple relatively inexpensive pattern generators operating at lower frequencies instead of a single expensive high-frequency test apparatus. The lower-cost components are multiplied in number to achieve the required testing capability, making the system economically viable for smaller enterprises
Solution Approach 2:
The patent creates a universal test apparatus that can handle various DUT operating frequencies by using multiple pattern generators that can be configured for different speed requirements, making the system adaptable and cost-effective across different testing scenarios
3Adaptability or versatility
If additional pattern generators are added to test faster memories, then the test apparatus can handle higher operating frequencies, but the apparatus size and cost continuously increase
Solution Approach 1:
The patent transitions from increasing frequency in a single component to adding multiple components operating in parallel. Instead of making one pattern generator faster, the system adds more pattern generators working simultaneously, achieving frequency adaptability through spatial arrangement rather than temporal speedup
4Ease of manufacture
If a low-speed test apparatus is used to test high-speed DUT, then cost is reduced, but the apparatus requires multiple pattern generators and becomes larger
Solution Approach 1:
The patent introduces a multiplexer as an intermediary component that combines the outputs of multiple pattern generators. This intermediary allows multiple lower-speed generators to function together as a unified high-speed test interface, managing the complexity through centralized control and signal routing
Data Source
AI summary
Provided is a test apparatus for testing a device under test (DUT), the apparatus operating at an operating frequency that is lower than an operating frequency of the DUT. The test apparatus includes a clock source which generates a clock according to the operating frequency of the test apparatus, a clock multiplier configured to multiply the generated clock source by a multiplication number which is set according to the operating frequency of the DUT and output a first clock for the DUT, a phase converter configured to shift a phase of the generated clock according to the multiplication number and output a plurality of second clocks having different phases, and a test pattern comparator configured to sequentially collect pieces of data from the DUT by sequentially applying the plurality of second clocks having different phases.