Clock Multiplier Feedback Delay Control to Prevent Phase Accumulation
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Solution Overview
Problem
Conventional clock multipliers accumulate frequency/phase differences between input and output clocks as the multiplying ratio increases, leading to errors in clock multiplication.
Innovation Solution
A clock multiplier design incorporating a phase/frequency detector, clock selector, and voltage-controlled delay line that adjusts the delay time of the input clock based on control signals generated from the phase/frequency difference, preventing accumulation of frequency/phase differences and eliminating jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the multiplying ratio is increased, then the output clock frequency is increased, but the frequency/phase difference between input and output clocks accumulates
Solution Approach 1:
The patent implements a feedback mechanism where the output clock is divided by N and fed back to a phase/frequency detector that compares it with the input clock. Based on the detected phase/frequency difference, control signals are generated to adjust the delay time of the voltage-controlled delay line, thereby correcting the accumulated frequency/phase difference and maintaining accurate clock multiplication even at high multiplying ratios.
Solution Approach 2:
The patent replaces traditional mechanical or conventional PLL-based clock multiplication mechanisms with a delay-locked loop approach using a voltage-controlled delay line. This substitution allows for more precise control of clock phase and frequency by electronically adjusting delay time based on feedback, eliminating the frequency/phase accumulation problem that occurs in conventional high-ratio multipliers.
2Adaptability or versatility
If the multiplying ratio is increased, then the clock multiplication capability is improved, but jitter accumulates
Solution Approach 1:
The phase/frequency detector continuously monitors the phase difference between the input clock and the divided output clock, generating feedback control signals that adjust the delay line. This feedback mechanism prevents jitter accumulation by continuously correcting phase deviations, allowing the system to achieve high multiplication ratios without the jitter problems that plague conventional approaches.
Solution Approach 2:
The patent employs a dynamic delay adjustment mechanism where the delay time of the voltage-controlled delay line is continuously adjusted based on real-time phase/frequency detection. This dynamic control allows the system to adapt to varying conditions and maintain stable clock multiplication at high ratios, preventing jitter accumulation through active correction rather than static design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures that the clock multiplier operates without accumulating frequency/phase differences between input and output clocks, even at increased multiplying ratios, and effectively eliminates accumulated jitter when the output clock precedes the input clock.
Implementation Method 1
The VCDL adjusts a delay time of the selected signal according to a control voltage that is generated based on the first control signal and the second control signal
Data Source
AI summary
A clock multiplier for multiplying an input clock by N includes a phase/frequency detector, a clock selector, and a voltage-controlled delay line. The phase/frequency detector generates a first control signal and a second control signal according to a frequency/phase difference between the input clock and a count signal indicating a signal that is generated by delaying the input clock N times. The clock selector selects one of the input clock and a feedback clock based on the input clock and the count signal. The voltage-controlled delay line adjusts a delay time of the selected signal according to a control voltage that is generated based on the first control signal and the second control signal, and outputs the feedback clock based on the adjusted signal. The clock multiplier operates without accumulating a frequency/phase difference between the input clock and the output clock when the multiplying ratio is increased.