Multi-Branch Clock Multiplier for Low Phase Noise
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Solution Overview
Problem
Existing frequency multiplying solutions for local oscillator signals in 5G millimeter-wave frequency bands suffer from high phase noise due to non-optimized sine-to-square-wave buffers, leading to increased costs with the use of high-frequency oscillators and independent reference clocks in MIMO systems.
Innovation Solution
A frequency multiplying circuit with N branches, each comprising a buffer and a frequency doubling circuit, coupled with second calibration delay circuits and an N-path phase combination circuit, which performs clock delay and phase combination to achieve a 2N-times frequency multiplied reference clock signal, optimizing phase noise without the need for high-frequency oscillators by using independent power and voltage sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single buffer is used for frequency multiplying, then device complexity is reduced, but phase noise quality deteriorates
Solution Approach 1:
The single buffer is segmented into N parallel buffer branches, each processing the reference clock signal independently. This segmentation allows the phase noise from each buffer to be uncorrelated, and when combined through the N-path phase combination circuit, the overall phase noise is reduced by a factor of N, thus improving phase noise quality while maintaining reasonable device complexity through modular replication.
2Measurement precision
If high-frequency oscillators are used to provide reference clocks, then frequency accuracy is improved, but cost increases
Solution Approach 1:
Instead of changing the oscillator frequency to achieve better performance, the invention changes the system architecture by using N parallel paths with frequency multiplication. The reference oscillator can remain at a lower frequency, but through the N-path phase combination and frequency doubling circuits, the effective output frequency and accuracy are improved without requiring expensive high-frequency oscillators.
3Reliability
If independent reference clocks are used for each transceiver unit in MIMO systems, then system performance is improved, but cost increases
Solution Approach 1:
The invention merges N buffer branches and their associated frequency doubling circuits into a single integrated frequency multiplying circuit. This allows multiple transceiver units to share a common reference clock source while maintaining the performance benefits of multiple independent paths, thus reducing cost by eliminating redundant oscillators while preserving system performance through the N-path architecture.
Data Source
AI summary
Frequency multiplying circuit for clock signal is provided, including N branches and an N-times frequency multiplying circuit, wherein each branch includes a buffer and a frequency doubling circuit, and the frequency doubling circuit doubles a frequency of a reference clock signal to obtain a frequency doubled reference clock signal, wherein the N-times frequency multiplying circuit includes: N second calibration delay circuits coupled to the N frequency doubling circuits respectively, wherein each second calibration delay circuit performs clock delay on the frequency doubled reference clock signal to obtain a clock delayed frequency doubled reference clock signal; and an N-path phase combination circuit coupled to the N second calibration delay circuits, and configured to perform phase combination on the N clock delayed frequency doubled reference clock signals to obtain a 2N-times frequency multiplied reference clock signal. Cost is reduced, and phase noise of a multi-times frequency multiplied reference clock signal is optimized.