Clock Multiplier Using PLL Filter Bias for Delay Cell Size Reduction
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Solution Overview
Problem
As operating frequencies in semiconductor devices increase, designing a clock generator that is insensitive to environmental changes, such as process, voltage, and temperature, while reducing the size of delay cells, remains a challenge in clock multiplier technologies.
Innovation Solution
A clock multiplier utilizing a phase-locked loop (PLL) with a bias generator, counter, selection circuit, flip-flop, phase comparator, delay controller, and variable delay circuit, which generates a phase-locked clock signal and oscillated control voltage to reduce the size of delay cells by adjusting delay times based on error signals, thereby stabilizing clock multiplication and reducing delay cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the delay cell size is reduced to lower power consumption, then power efficiency is improved, but the delay precision and stability deteriorate
Solution Approach 1:
The delay circuit is divided into multiple delay cells connected in series, each contributing a portion of the total delay. This segmentation allows the use of smaller individual cells while maintaining overall delay precision through cumulative effect and controlled adjustment of each segment.
Solution Approach 2:
The invention dynamically adjusts the delay amount by changing parameters such as the number of active delay cells or their individual delay characteristics. This allows optimization of delay precision without requiring each cell to be large, thereby reducing overall power consumption while maintaining required delay accuracy.
2Area of stationary object
If the delay cell size is reduced to minimize circuit area, then area efficiency is improved, but the delay stability and environmental insensitivity worsen
Solution Approach 1:
Multiple small delay cells are arranged in series to achieve the required total delay. This segmentation reduces the area of each individual cell while the cumulative delay of all cells maintains the required stability and precision, resolving the contradiction between area reduction and stability maintenance.
Solution Approach 2:
The phase comparator generates an error signal based on the phase difference between input and feedback clocks, which is then used to adjust the delay amount. This feedback mechanism compensates for environmental variations and maintains delay stability even with reduced cell size, thereby preserving environmental insensitivity.
3Measurement precision
If the delay amount is increased to improve clock multiplication accuracy, then multiplication precision is improved, but the circuit complexity and power consumption increase
Solution Approach 1:
The delay circuit is segmented into multiple controllable delay cells, allowing the required delay amount to be achieved through combination of simpler units. This segmentation improves multiplication accuracy by enabling fine-grained delay adjustment without proportionally increasing overall circuit complexity.
Solution Approach 2:
The delay amount is made dynamically adjustable based on the error signal from the phase comparator. This dynamic adjustment allows the circuit to achieve high multiplication accuracy by adapting the delay amount to actual phase differences, rather than requiring a fixed complex delay structure.
Data Source
AI summary
A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays a reference signal by a first delay time and by a second time that is longer than the first delay time, and generates a first feedback signal corresponding to the first delay time, and a second feedback signal corresponding to the second delay time. Therefore, a clock multiplier may reduce the size of a delay cell and may be designed to be insensitive to changes in environmental conditions, such as a process, a voltage, a temperature, and so on.