Multi-Feedback Clock Multiplier for Faster PLL Lock and Lower Jitter
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Solution Overview
Problem
The low root reference clock frequency in phase-locked loops (PLLs) limits PLL bandwidth, leading to increased PLL lock and settling times, higher jitter, and increased noise and power consumption, while cascading additional PLLs introduces additional costs and complexities.
Innovation Solution
A multi-feedback circuit that compares a duty cycle corrected reference clock to control identical delay lines, generating a new clock with a higher frequency, which is used as a reference for the PLL or multiplying delay locked loop, thereby reducing jitter and increasing PLL bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the root reference clock frequency is increased to improve PLL bandwidth and reduce lock time, then PLL performance is improved, but power consumption and noise increase
Solution Approach 1:
A duty cycle correction circuit is introduced as an intermediary component between the reference clock source and the PLL. This circuit corrects duty cycle errors in the reference clock signal, enabling the PLL to achieve better performance at lower frequencies without requiring higher power consumption, thus resolving the contradiction between PLL bandwidth and power consumption
Solution Approach 2:
The invention changes the parameter of reference clock frequency from the conventional low frequency (e.g., 38.4 MHz) to a higher frequency (e.g., 76.8 MHz or 153.6 MHz) by using a frequency multiplier. This parameter change allows the PLL to operate with higher bandwidth and faster lock times while the duty cycle correction ensures clean signals, avoiding the need for even higher frequencies that would consume more power
2Loss of time
If the root reference clock frequency is increased to reduce PLL lock time, then settling time is reduced, but output clock jitter increases
Solution Approach 1:
The duty cycle correction circuit serves as an intermediary that cleans up the reference clock signal by correcting duty cycle errors. This ensures that even at higher frequencies, the signal quality remains high, allowing the PLL to achieve fast lock times without introducing excessive jitter in the output clock
Solution Approach 2:
The duty cycle correction is applied in advance to the reference clock signal before it enters the PLL. By pre-correcting the duty cycle errors, the PLL receives a clean signal that enables fast locking without the jitter that would otherwise be introduced by operating at higher frequencies
3Speed
If the root reference clock frequency is increased to improve PLL bandwidth, then noise filtering is improved, but phase noise increases
Solution Approach 1:
The duty cycle correction circuit acts as an intermediary that prepares a clean reference clock signal with correct duty cycle. This enables the PLL to achieve higher bandwidth for better noise filtering while the clean input signal prevents excessive phase noise generation, resolving the contradiction between bandwidth and phase noise
4Speed
If cascading additional PLLs is used to achieve higher reference clock frequency, then frequency multiplication is achieved, but device complexity increases
Solution Approach 1:
The invention extracts and corrects only the duty cycle error component from the reference clock signal using a dedicated correction circuit, rather than cascading multiple PLLs. This approach achieves frequency multiplication with simpler circuitry, reducing device complexity while maintaining the desired reference clock frequency
Solution Approach 2:
A duty cycle correction circuit is introduced as an intermediary between the reference clock source and the PLL, providing a clean multiplied frequency signal without requiring cascaded PLLs. This intermediary approach achieves frequency multiplication with reduced circuit complexity
Data Source
AI summary
A multi-feedback circuit that compares a duty cycle corrected reference clock fREF, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fREF with approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.