Clock Frequency Multiplier Using Threshold Calibration for Low Jitter
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Solution Overview
Problem
Highly integrated microprocessors face challenges with increased clock skew and power density, necessitating a method to generate high-frequency clock signals with low jitter and low power consumption.
Innovation Solution
An apparatus and method that includes an oscillation circuit, control signal generation circuit, threshold value generation circuit, and clock output circuit, which compares an initial oscillator signal with reference and threshold values to generate a control signal, calibrating threshold values to produce an output clock signal with desired frequency, duty cycle, and pulse width, thereby multiplying the frequency of the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher integration is implemented to increase microprocessor performance, then processing capability is improved, but clock skew and jitter increase
Solution Approach 1:
The patent segments the clock signal generation into multiple independent oscillation circuits, each generating clock signals for specific functional blocks. This segmentation isolates clock skew issues to local regions rather than affecting the entire system, thereby maintaining reliability while enabling higher integration for improved processing capability.
Solution Approach 2:
The patent implements preliminary calibration of oscillation circuits during startup or low-load periods to pre-adjust frequency and phase parameters. This preliminary action ensures that when the processor operates at high performance levels, the clock signals are already optimized, preventing clock skew and jitter from degrading reliability during intensive processing.
2Productivity
If clock frequency is increased to improve performance, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent employs dynamic frequency adjustment where each oscillation circuit can independently adjust its operating frequency based on the actual performance requirements of its associated functional block. This dynamic adaptation allows the system to achieve high processing speed when needed while reducing power consumption during lower-demand operations, resolving the contradiction between speed and energy usage.
Solution Approach 2:
The patent changes operational parameters (frequency, duty cycle, voltage) of the oscillation circuits to optimize the trade-off between processing speed and power consumption. By adjusting these parameters dynamically, the system can operate at high frequencies for improved speed when necessary, while operating at lower frequencies to reduce power consumption during normal operation.
3Productivity
If higher power density is used to improve performance, then processing capability is improved, but heat generation and power management difficulty increase
Solution Approach 1:
The patent segments the power distribution and clock generation into multiple independent oscillation circuits, each serving specific functional blocks. This segmentation allows for localized power management and heat dissipation, preventing concentrated heat generation that would occur with monolithic high-power designs, thereby enabling high processing capability while managing temperature effectively.
Solution Approach 2:
The patent utilizes periodic calibration and adjustment of oscillation parameters to maintain optimal efficiency. By periodically adjusting operating parameters, the system ensures that power is used efficiently during high-performance periods, reducing waste heat generation while maintaining processing capability.
Data Source
AI summary
An apparatus and method for multiplying frequency of a clock signal are provided, wherein the apparatus provides an initial oscillator signal, compares the initial oscillator signal with a reference signal to generate a first control signal, selectively outputs one of at least one lower threshold value and at least one upper threshold value from a threshold value generation circuit to a clock output circuit according to at least the first control signal, and updates an output clock signal through a digital and logical module processing the comparison of the initial oscillator signal and the selected one of the at least one upper and lower threshold values and the comparison of the initial oscillator signal and a low level signal.