Clock Multiplexer Output Gating for Glitch-Free Source Switching
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Solution Overview
Problem
Existing clock switching systems often generate glitches when transitioning between different clock sources, particularly in multiplexer circuits, which can lead to errors in applications requiring glitch-free signals.
Innovation Solution
Incorporating a glitch suppression circuit that outputs either the selected clock signal or a logic low signal when a glitch suppression signal is activated, effectively suppressing glitches by tying the output signal to ground during transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multiplexer circuit is used to switch between clock signal sources, then the ability to select from multiple clock sources is improved, but glitches are generated during transitions between clock signals
Solution Approach 1:
A glitch suppression circuit is introduced as an intermediary component between the multiplexer output and the system clock input. This circuit receives both the multiplexer output signal and a glitch suppression signal, and only passes through the clock signal when the suppression signal indicates it is safe to do so, thereby mediating the harmful glitch effect while preserving the multiplexer's switching capability
Solution Approach 2:
The system applies preliminary anti-action by generating a glitch suppression signal that anticipates and counteracts potential glitches before they can affect the system clock. The suppression circuit is configured to block or suppress the multiplexer output during transition periods when glitches are likely to occur, preventing the harmful effect before it propagates to the system clock
2Productivity
If clock signal switching is implemented to match processing rate with demand, then power saving and processing efficiency are improved, but signal integrity is degraded due to glitch generation
Solution Approach 1:
The glitch suppression circuit serves as a mediator that allows the clock switching functionality to operate for power saving and efficiency purposes while simultaneously protecting signal integrity. It selectively passes or blocks the multiplexer output based on the suppression signal state, enabling safe clock transitions without compromising reliability
Solution Approach 2:
The system employs feedback mechanisms where the glitch suppression signal is generated based on the state of the multiplexer output and transition timing. This feedback loop allows the suppression circuit to dynamically adjust its behavior, blocking signals during problematic transitions while allowing them during safe transitions, thus maintaining both productivity and reliability
Data Source
AI summary
Certain aspects of the present disclosure provide an input clock switching system, including: a clock source configured to output a reference clock signal; a clock generator circuit connected to the clock source and configured to output a plurality of input clock signals based on the reference clock signal; an output clock multiplexer, configured to: receive the plurality of input clock signals; receive an output clock selection signal; and output a first clock signal, wherein the first clock signal is one of the input clock signals; and a glitch suppression circuit, configured to: receive the first clock signal; receive a glitch suppression signal; output a clock output signal, wherein the clock output signal is: the first clock signal when the glitch suppression signal is in a first state; and a logic low signal when the glitch suppression signal is in a second state.