Clock Distribution Network With On-Demand Peripheral Clocking
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Solution Overview
Problem
Digital processing systems require high power consumption for global clock trees, leading to reduced battery life in mobile devices due to the need for synchronized clock signals across all units.
Innovation Solution
A clock distribution network that generates processor and peripheral clock signals with different edges, allowing peripheral units to operate independently and request clock signals only when needed, eliminating the need for a global clock tree and reducing power consumption by enabling separate, demand-based communication links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global clock tree is established to synchronize all processing units and peripheral units, then data exchange between units is enabled, but static and dynamic power consumption increases significantly
Solution Approach 1:
The patent divides the global clock tree into multiple independent local clock trees, each serving specific processing units or peripheral units. This segmentation allows each clock tree to operate independently, enabling data exchange within each local tree without requiring all units to be synchronized globally, thereby reducing the power consumption associated with maintaining a comprehensive global clock distribution network.
Solution Approach 2:
The patent implements periodic activation of clock signals based on demand. Instead of continuously providing clock signals to all units through a global clock tree, the system activates clock signals periodically or on-demand for specific units that need to exchange data, reducing dynamic power consumption while maintaining data exchange capability when needed.
2Reliability
If all processing units and peripheral units operate on the same global clock tree, then synchronized data exchange is achieved, but battery lifetime is reduced due to high power consumption
Solution Approach 1:
By segmenting the unified global clock tree into multiple independent local clock trees, the patent enables synchronized data exchange within each local group while allowing other groups to remain inactive or operate at lower power modes, thereby extending battery lifetime without compromising data exchange reliability within active segments.
Solution Approach 2:
The patent applies local quality by allowing different regions or groups of units to have different clocking characteristics. Each local clock tree can be optimized for its specific function or activity level, with clock signals activated or deactivated based on local demand, rather than uniformly maintaining global synchronization across all units, thus reducing overall power consumption and extending battery life.
3Adaptability or versatility
If a global clock tree is implemented to enable data transmission between processing units and peripheral units, then communication capability is ensured, but the system requires high static and dynamic power consumption
Solution Approach 1:
The patent segments the global clock distribution network into multiple local clock trees, each capable of supporting data transmission within its local group. This segmentation maintains communication capability for units within the same local tree while eliminating the energy consumption associated with maintaining clock signals for units that are not currently exchanging data, thereby reducing overall energy loss.
Solution Approach 2:
The patent introduces dynamic clock gating mechanisms that allow clock signals to be selectively enabled or disabled for different local clock trees based on actual communication needs. This dynamic approach maintains adaptability and versatility of the system by enabling communication when required while minimizing energy consumption during idle periods or when fewer units need to communicate.
Data Source
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AI summary
The present disclosure relates to a clock distribution network (10), comprising: - a clock generator (14) configured to generate at least a processor clock signal and at least a first peripheral clock signal, the clock generator (14) further comprises at least a processor clock output (31), a first peripheral clock output (32) and a first clock request input (42), - a processing unit (16) connected to the processor clock output (31) and configured to operate on a rising edge of the processor clock signal receivable via the processor clock output (31), - at least a first peripheral unit (22) connected to the first peripheral clock output (32) and connected to the first clock request input (42) of the clock generator (14), wherein the at least first peripheral unit (22) is configured to operate on a falling edge of the first peripheral clock signal received via the first peripheral clock output (32), - wherein the at least first peripheral unit (22) via the first clock request input (42) is operable to trigger the clock generator (14) to transmit the first peripheral clock signal via the first peripheral clock output (32).