Clock Network Analysis via Formal Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of clock networks in integrated circuits makes it difficult for designers and verification engineers to understand, implement, and verify clock and clock relations, often leading to manual and error-prone processes, with available tools providing incomplete or convoluted information.
Innovation Solution
The use of formal verification techniques to extract valid clock modes from a hardware description of a clock network, involving parametric liveness property checking to infer valid clock modes based on configuration signals, and generating abstracted functional views to facilitate understanding and verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual processes are used to analyze and verify clock networks, then flexibility and adaptability are maintained, but error rates increase and productivity decreases
Solution Approach 1:
The patent replaces manual mechanical analysis processes with automated formal verification tools. The system automatically extracts clock modes, generates abstracted functional views, and performs verification without human intervention, thereby eliminating human errors while maintaining high productivity through automation.
Solution Approach 2:
The system changes the state of clock network analysis from manual inspection to automated formal verification. By transforming the verification process into a systematic algorithmic approach with defined parameters and rules, the system achieves both high reliability through comprehensive checking and high productivity through automation.
2Manufacturing precision
If detailed hardware descriptions are used to specify clock networks, then implementation precision is improved, but understanding and visualization become more difficult
Solution Approach 1:
The patent extracts essential clock mode information from complex hardware descriptions and presents it in simplified abstracted functional views. This extraction process separates the detailed implementation information from the functional understanding, allowing engineers to comprehend clock relationships without being overwhelmed by the full hardware description complexity.
Solution Approach 2:
The system segments the complex clock network analysis into distinct components: clock mode extraction, abstracted functional view generation, and verification. This segmentation allows the detailed hardware description to be processed in manageable portions, maintaining implementation precision while reducing the cognitive load for understanding and visualization.
3Productivity
If existing IP blocks are integrated into designs, then productivity is improved, but knowledge of clock relations is lost
Solution Approach 1:
The patent implements feedback mechanisms that automatically extract and verify clock mode information from integrated IP blocks. The system provides feedback about clock relations, modes, and dependencies to the designer, ensuring that no critical information is lost during the integration process and enabling rapid design iterations.
Solution Approach 2:
The system acts as an intermediary between the integrated IP blocks and the designer. It automatically extracts clock mode information from the IP blocks and presents it in an accessible format, serving as a bridge that preserves critical clock relation information while maintaining the productivity benefits of IP integration.
4Extent of automation
If available tools are used to analyze clock networks, then some automation is achieved, but information completeness and clarity remain insufficient
Solution Approach 1:
The patent creates a universal verification system that handles multiple aspects of clock network analysis: extraction, visualization, verification, and generation of abstracted functional views. This multi-functional approach ensures information completeness by addressing all aspects of clock mode analysis through a single comprehensive system rather than multiple specialized tools.
Data Source
AI summary
Formal verification techniques are used to extract valid clock modes from a hardware description of the clock network. In one aspect, the clock network includes primary clocks and configuration signals as inputs, and also includes derived clocks within the clock network. The derived clocks are configurable for different clock modes according to the values of the configuration signals. A parametric liveness property checking is applied to the derived clocks, where the configuration signals are parameters for the parametric liveness property checking. The parametric liveness property checking infers which values of the configuration signals result in valid clock modes for the derived clocks.