Clock Distribution Network With Local Trees for Lower Power
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Solution Overview
Problem
Digital processing systems face high power consumption due to the need for global clock trees, which require numerous buffers and inverters, leading to reduced battery life in mobile devices.
Innovation Solution
A clock distribution network that operates on different clock edges for processing and peripheral units, eliminating the need for a global clock tree by allowing individual units to request clock signals independently, reducing power consumption through local clock trees and direct communication links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global clock tree is implemented to synchronize all processing and peripheral units, then data exchange between units is enabled, but power consumption increases due to the need for numerous buffers and inverters
Solution Approach 1:
The patent divides the global clock tree into separate local clock trees for different unit types. Processing units have one clock tree while peripheral units have another clock tree, allowing independent clock distribution and reducing the need for buffering and inversion across the entire system.
Solution Approach 2:
The patent utilizes different clock edges (rising edge for processing units, falling edge for peripheral units) to enable data exchange without requiring continuous synchronization. This periodic action on opposite edges allows asynchronous communication between units while reducing power consumption.
2Reliability
If all flip-flops in a global clock tree toggle at the same time to enable data exchange, then synchronization is achieved, but static and dynamic power consumption increases
Solution Approach 1:
The patent segments the synchronized toggling into separate groups: processing unit flip-flops toggle on rising edges while peripheral unit flip-flops toggle on falling edges. This segmentation maintains functional synchronization for data exchange while reducing simultaneous switching power consumption.
Solution Approach 2:
The patent inverts the clock edge used by peripheral units relative to processing units. While processing units use rising edges, peripheral units use falling edges, creating an inverted timing relationship that reduces simultaneous toggling and power consumption while maintaining data exchange capability.
3Adaptability or versatility
If a global clock tree is established to enable communication between processing and peripheral units, then data transmission is possible, but the number of hardware components (buffers, inverters) increases
Solution Approach 1:
The patent segments the clock distribution into separate networks for processing units and peripheral units. This eliminates the need for a comprehensive global clock tree spanning all units, reducing the number of required buffers and inverters while maintaining data transmission capability through edge-differentiated synchronization.
Data Source
AI summary
A clock distribution network (10) including a clock generator (14) configured to generate at least a processor clock signal and at least a first peripheral clock signal, the clock generator including a processor clock output (31), a first peripheral clock output (32) and a first clock request input (42). A first peripheral unit (22) via a first clock request input (42) is operable to trigger the clock generator (14) to transmit the first peripheral clock signal via the first peripheral clock output (32).