Clock Network Meta-Synthesis for Synchronous Distribution
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Solution Overview
Problem
Designing a clock distribution network in integrated circuits that ensures synchronicity of clock arrival times is challenging, requiring manual iterations and tedious adjustments of design parameters, often resulting in unsatisfactory results due to reliance on default software tool specifications.
Innovation Solution
A method involving a meta-synthesis tool that receives design specifications, determines the topology and design parameters of the clock network, and generates a tool specification file to synthesize a clock network that synchronously distributes the clock signal to endpoints, reducing the need for manual trial and error by ensuring consistent buffer types and fanout across levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual iteration and adjustment of design parameters is performed to achieve synchronous clock arrival times, then clock network synchronicity is improved, but design time and complexity increase significantly
Solution Approach 1:
The patent applies preliminary action by performing a two-phase synthesis process where the first phase pre-determines the clock network topology (hierarchy, buffer types, fanout) before the second phase synthesizes the actual clock network. This preliminary topology determination ensures that design parameters are optimized for synchronous clock arrival times before implementation, eliminating the need for manual trial-and-error iterations during the synthesis phase.
Solution Approach 2:
The patent segments the clock network synthesis process into two distinct phases: (1) topology synthesis that determines the hierarchical structure, buffer types, and fanout values, and (2) clock network synthesis that implements the actual clock distribution based on the predetermined topology. This segmentation allows each phase to focus on specific optimization goals, with the topology phase ensuring synchronicity requirements are met before implementation.
2Ease of operation
If default software tool specification is used for clock network synthesis, then synthesis process is simplified, but clock arrival time synchronicity deteriorates
Solution Approach 1:
The patent performs preliminary determination of optimal design parameters (topology, buffer types, fanout) based on synchronous clock arrival time requirements before invoking the standard EDA tool. This preliminary action ensures that when the simplified default synthesis process is used, it operates with pre-optimized parameters that guarantee clock synchronicity, thus maintaining both ease of operation and manufacturing precision.
Solution Approach 2:
The patent introduces an intermediary topology synthesis process that acts as a mediator between the design requirements and the standard EDA tool synthesis. This intermediary phase translates high-level synchronicity requirements into specific design parameters (topology, buffer types, fanout) that are then passed to the synthesis tool, ensuring that the simplified synthesis process produces results that meet the clock arrival time requirements.
3Manufacturing precision
If multiple iterations of parameter adjustment are performed, then clock network synchronicity is improved, but device complexity and manual effort increase
Solution Approach 1:
The patent segments the complex design process into two distinct synthesis phases with clearly defined responsibilities. The first phase (topology synthesis) handles all the complex parameter determination (topology, buffer types, fanout) automatically, while the second phase (clock network synthesis) simply implements the predetermined topology. This segmentation eliminates the need for multiple manual parameter adjustment iterations and reduces design process complexity.
Solution Approach 2:
The topology synthesis process automatically determines the optimal design parameters (topology, buffer types, fanout) based on the requirement for synchronous clock arrival times, without requiring manual intervention or iteration. This self-service capability eliminates the need for designers to perform multiple rounds of parameter adjustment, thereby reducing both device complexity and manual effort.
Data Source
AI summary
In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.