Clock Distribution Network With Power-Noise Phase Compensation
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Solution Overview
Problem
As semiconductor apparatuses operate at higher speeds, variations in process, voltage, and temperature (PVT) lead to clock signal jitter and insufficient setup and hold margins due to unmatched DQ-DQS schemes, causing synchronization issues between clock signals and data.
Innovation Solution
A clock generating circuit comprising a buffer circuit, a voltage control circuit, and a compensating circuit that adjusts the phase and voltage levels of input clock signals based on detected power voltage changes, using complementary control voltages to stabilize output clock signals and maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operation speed of the computer system is increased, then the productivity is improved, but the clock signal becomes susceptible to jitter and delay time variation due to PVT variations
Solution Approach 1:
The patent implements a feedback mechanism where the delay time of the clock signal is measured and used to adjust the phase of the clock signal through a phase adjustment circuit. This closed-loop feedback system continuously compensates for delay variations caused by PVT changes, maintaining stable clock timing even at high operation speeds.
Solution Approach 2:
The patent dynamically adjusts the phase of the clock signal based on detected delay time variations. By changing the phase parameter in response to PVT conditions, the system compensates for timing errors and maintains reliable clock synchronization without reducing operation speed.
2Productivity
If the unmatched DQ-DQS scheme is used for high-speed operation, then the productivity is improved, but the setup and hold margins become insufficient
Solution Approach 1:
The system measures the actual delay time of the clock signal and uses this feedback to adjust the phase accordingly. This ensures that setup and hold timing requirements are met even when using unmatched DQ-DQS paths for high-speed operation.
Solution Approach 2:
The phase adjustment is performed in advance based on predicted or measured delay characteristics. By pre-adjusting the clock phase before data transmission, the system ensures adequate setup and hold margins are established before the actual data sampling occurs.
3Reliability
If the phase of the clock signal is adjusted to compensate for delay, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent uses a feedback-based phase adjustment approach where delay measurement and phase correction are integrated into the existing clock distribution network. This automated feedback mechanism improves synchronization accuracy without requiring complex manual calibration circuits.
Solution Approach 2:
The system performs self-adjustment of the clock phase by automatically measuring its own delay characteristics and correcting the phase accordingly. This self-service capability reduces the need for external calibration equipment and complex control circuits.
Data Source
AI summary
A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.