Clock Network Optimization via Potential Slack Allocation
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Solution Overview
Problem
Conventional circuit optimization and clock tree synthesis techniques for IC designs are inefficient due to their long processing times and poor quality results, especially in large and complex integrated circuit (IC) designs, as they do not effectively utilize potential slack in clock arrival times, leading to increased area and dynamic power in the clock network and potential hold timing violations.
Innovation Solution
Optimizing the clock network during logic synthesis and placement by determining and allocating potential setup-timing-slacks across sequential cells, balancing clock skew between timing paths, and applying these allocations to improve the overall design performance, thereby enhancing the optimization of IC designs before clock tree synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional circuit optimization techniques are used to optimize data paths during logic synthesis and placement, then data path timing is improved, but the clock network complexity increases and hold timing violations occur
Solution Approach 1:
The patent applies preliminary action by allocating potential setup timing slacks to sequential cells before performing data path optimization. This pre-allocation of clock arrival times prepares the design to absorb timing variations without increasing clock network complexity or causing hold violations during subsequent optimization stages.
Solution Approach 2:
The patent changes the parameter of clock arrival times at sequential cells by allocating potential setup slacks. This parameter modification allows the clock network to accommodate data path optimizations without increasing complexity or introducing hold timing violations.
2Speed
If data path optimization is performed aggressively to meet timing goals, then timing performance is improved, but leakage power and area increase due to recovery of positive slack
Solution Approach 1:
The patent changes the parameter of clock arrival times by allocating potential setup slacks to sequential cells. This allows the optimization process to achieve timing goals without aggressively optimizing data paths that would otherwise increase leakage power and area through positive slack recovery.
3Manufacturing precision
If clock arrival times are optimized after data path optimization, then timing constraints are met, but the range of possibilities is limited by available positive slack
Solution Approach 1:
The patent applies preliminary action by allocating potential setup slacks to sequential cells before data path optimization. This pre-allocation expands the range of possibilities for timing optimization by considering future slack availability, rather than being limited by current positive slack after aggressive data path optimization.
Data Source
AI summary
During logic synthesis and placement optimization, designs are aggressively optimized for timing, power, and area but only the data paths are modified and the clock network is assumed to be “ideal” and fixed. The described embodiments optimize the clock network as well as the data path logic during the logic synthesis and placement optimization stages, thereby improving the overall performance of the design.