Digital Clock Generator Noise Rejection for Stable Frequency

Solution Overview

Problem

Current clock generation technologies face challenges in maintaining accurate frequency due to noise issues, particularly with analog solutions being large and prone to variations in process, voltage, and temperature, which affect the stability and area efficiency of noise rejection circuits.

Innovation Solution

A digital noise rejection circuit utilizing a higher frequency internal reference clock and a digital counter to generate a filtered clock signal, where the state machine ensures only the first edge within a predetermined time span is accepted, reducing long-term frequency drift and noise impact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If analog RC filters are used to filter noise from clock signals, then noise filtering capability is improved, but circuit area and delay variation increase

Engineering Contradiction:

Improvenoise filtering capabilityVSAvoidcircuit area

Core Design Contradiction:

Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent replaces the mechanical analog RC filter system with a digital noise rejection circuit that uses a state machine, digital counter, and logic gates to achieve noise filtering. This substitution eliminates the need for physical resistors and capacitors, significantly reducing circuit area while maintaining filtering effectiveness through digital logic operations that detect and reject noise pulses.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the filtering approach from continuous analog parameter adjustment to discrete digital parameter control. The digital counter uses a predetermined count value (e.g., 4) to define the noise rejection window, allowing precise control of filtering characteristics through digital parameters rather than analog component values, thereby stabilizing delay against PVT variations.

Inventive Principle:

Principle #35Parameter changes

2Object-affected harmful factors

If analog RC filters are used to filter noise from clock signals, then noise filtering capability is improved, but delay stability deteriorates

Engineering Contradiction:

Improvenoise filtering capabilityVSAvoiddelay stability

Core Design Contradiction:

Object-affected harmful factorsVSStability of the object's composition

Solution Approach 1:

The patent replaces the mechanical analog RC filter system with a digital noise rejection circuit that uses a state machine, digital counter, and logic gates to achieve noise filtering. This substitution eliminates the need for physical resistors and capacitors, significantly reducing circuit area while maintaining filtering effectiveness through digital logic operations that detect and reject noise pulses.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

Instead of trying to prevent delay variation through careful analog component selection, the patent inverts the approach by using digital logic with fixed propagation delays. The state machine and counter use predetermined count values to establish stable timing characteristics that are inherently resistant to PVT variations, making the delay stable by design rather than by component selection.

Inventive Principle:

Principle #13The other way round (Inversion)

3Area of stationary object

If digital noise rejection circuit is used, then area and power consumption are reduced, but noise filtering capability must be maintained

Engineering Contradiction:

Improvecircuit areaVSAvoidnoise filtering capability

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent replaces the mechanical analog RC filter system with a digital noise rejection circuit that uses a state machine, digital counter, and logic gates to achieve noise filtering. This substitution eliminates the need for physical resistors and capacitors, significantly reducing circuit area while maintaining filtering effectiveness through digital logic operations that detect and reject noise pulses.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The state machine monitors the clock signal and uses feedback from the digital counter to determine whether to pass or reject signal edges. When the counter reaches the predetermined value within a clock cycle, the state machine generates a reset signal that prevents noise-induced edges from propagating to the output, thereby maintaining noise filtering capability through intelligent feedback control.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11586238B1Clock generator with noise rejection circuit

Publication Date: 2023.02.21 NXP BV

AI summary

A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.