Programmable Clock Noise Shaping for High-Speed Serial Links
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Solution Overview
Problem
As data rates increase, phase noise in clock signals becomes a significant issue for serial links, particularly at gigabit-per-second rates, affecting the accuracy and reliability of clock signals in integrated circuits.
Innovation Solution
A clock circuit with a programmable filter and phase lock loop is used to shape and suppress noise in the input clock signal, ensuring the output clock signal meets phase noise requirements for high-speed serial links, incorporating a buffer to provide differential clock signals and a programmable counter for frequency translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rate is increased to gigabit-per-second or more, then productivity is improved, but phase noise in clock signal worsens
Solution Approach 1:
A filter is introduced as an intermediary component between the input clock signal source and the phase lock loop. This filter shapes the noise spectrum of the clock signal, pushing phase noise away from the carrier frequency and into frequency ranges that are less critical for high-speed serial link operation, thereby enabling gigabit-per-second data rates while controlling phase noise impact
2Device complexity
If conventional phase lock loop is used without noise shaping, then device complexity is reduced, but phase noise performance worsens at high data rates
Solution Approach 1:
The filter performs preliminary noise shaping on the input clock signal before the signal enters the phase lock loop. By pre-shaping the noise spectrum in advance, the phase lock loop receives a clock signal with already-optimized phase noise characteristics, enabling the system to meet gigabit-per-second phase noise requirements without requiring complex modifications to the phase lock loop itself
Data Source
AI summary
A method and apparatus for clock signal noise shaping are described. Embodiments of a clock circuit include a filter coupled to receive an input clock signal and to provide an output clock signal. The filter filters noise of the input clock signal to shape the noise to provide the output clock signal. In a method for adjustment of phase noise, input clock signaling having the phase noise is obtained, and the input clock signal is filtered to adjust the phase noise to provide output clock signaling.


