Clock Circuit Noise Compensation for Stable Timing
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Solution Overview
Problem
Existing clock circuits in integrated circuits are complex and costly due to the need to address variations in temperature, ground noise, and power noise, which affect the timing of the output clock signal, and there is a need for a more efficient approach to generate a uniform output clock signal.
Innovation Solution
A clock integrated circuit design that includes a timing circuit alternating between two reference signals at a rate determined by a time constant, with a level switching circuit comparing the outputs to determine the clock signal, and a reference circuit selectively coupled to the varying noise signal to store its value, minimizing noise phase and reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffer circuits with active loads, independent bias circuitry, and bias circuitry are added to decouple power fluctuations from the clock signal, then the clock signal becomes tolerant to power noise, but the circuit complexity and die area increase significantly
Solution Approach 1:
The patent extracts the noise signal from the reference voltage and processes it separately through a dedicated noise processing circuit. The noise processing circuit generates a compensated reference signal that counteracts the noise effects, allowing the clock circuit to tolerate power and ground noise without requiring complex buffer circuits or independent bias circuitry for each clock element.
Solution Approach 2:
The patent introduces a noise processing circuit as an intermediary between the noisy reference voltage and the clock circuit elements. This intermediary circuit processes the noise signal and generates a compensated reference signal that mediates the interaction between noise and clock timing, enabling noise tolerance with minimal additional complexity.
2Stability of the object's composition
If buffer circuits with active loads are added to isolate power fluctuations, then the clock signal stability improves, but the die area and manufacturing cost increase
Solution Approach 1:
The patent extracts and processes the noise component separately through a noise processing circuit that generates a compensated reference signal. This approach achieves clock signal stability without requiring large buffer circuits with active loads, thereby reducing die area while maintaining uniformity.
Solution Approach 2:
The noise processing circuit serves multiple functions: it processes ground noise, processes power noise, and generates compensated reference signals for multiple clock circuit elements. This multi-functional approach achieves stability with minimal die area by avoiding redundant buffer circuits for each element.
3Measurement precision
If independent bias circuitry is added to each clock element to prevent power noise coupling, then the clock timing precision improves, but the device complexity and cost increase
Solution Approach 1:
The patent extracts the noise signal and processes it centrally through a noise processing circuit that generates a unified compensated reference signal. This centralized noise processing approach maintains clock timing precision without requiring independent bias circuitry for each clock element, thereby reducing overall circuit complexity.
Solution Approach 2:
The patent merges the noise processing function into a single noise processing circuit that serves all clock elements. Instead of having separate bias circuits for each element, the compensated reference signal is distributed to multiple clock elements, achieving timing precision with reduced complexity through functional consolidation.
Data Source
AI summary
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.