Clock Frequency Control Using Temperature-Corrected Noise Detection

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Solution Overview

Problem

Conventional power supply noise monitors in semiconductor integrated circuits face accuracy issues in controlling clock signal frequency due to temperature dependence of delay time, leading to potential timing errors and inefficient noise management.

Innovation Solution

A control circuit with a noise detection circuit comprising two delay circuits and a control unit that adjusts the clock signal frequency based on noise detection results and temperature corrections, using a temperature correction code table to maintain a constant summed delay time across varying temperatures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional power supply noise monitor using delay time change is used to control clock signal frequency, then power supply noise detection capability is improved, but temperature dependence of delay time reduces measurement precision

Engineering Contradiction:
Improvepower supply noise detection accuracyVSAvoidclock frequency control accuracy under temperature variation
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the measured delay time is fed back to adjust the clock signal frequency. The delay time measurement unit continuously monitors the delay time, and when it exceeds a threshold, the control unit adjusts the clock frequency accordingly, creating a closed-loop system that adapts to real-time conditions.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the operating parameters of the delay circuit by adjusting the clock signal frequency based on measured delay time. When delay time increases due to power supply noise, the system increases the clock frequency to compensate, effectively changing the temporal parameters of signal propagation to maintain timing accuracy.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the clock signal frequency is reduced to avoid timing errors during power supply noise, then timing error occurrence is reduced, but productivity of the semiconductor integrated circuit deteriorates

Engineering Contradiction:
Improvetiming error preventionVSAvoidcircuit operation speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic clock frequency adjustment rather than static reduction. The clock signal frequency is continuously adapted based on real-time delay time measurements, allowing the system to operate at high speeds when conditions permit and only reduce frequency when actually needed to prevent timing errors.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies partial action by adjusting only the clock frequency parameter rather than reducing overall circuit operation. The delay time threshold is set to trigger adjustment only when necessary, allowing the circuit to maintain maximum productivity during normal operation while providing sufficient correction during noise events.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If the delay time is increased to improve noise detection sensitivity, then power supply noise detection capability is improved, but the propagation delay of signals through the circuit increases

Engineering Contradiction:
Improvenoise detection sensitivityVSAvoidsignal propagation delay
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the delay circuit into multiple stages or paths, allowing selective measurement of delay time in specific segments rather than increasing overall circuit delay. This enables localized noise detection without affecting global signal propagation timing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary measurement mechanism that monitors delay time without adding significant delay to the main signal path. The delay time measurement unit operates in parallel or uses sampling techniques to assess delay characteristics without becoming part of the critical signal propagation path.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10720908B2Control circuit and control method
Publication Date: 2020.07.21 FUJITSU LTD
  • US10720908B2 patent drawing
  • US10720908B2 patent drawing
  • US10720908B2 patent drawing

AI summary

A noise detection circuit includes a first delay circuit which has a propagation delay of a first delay time when a signal propagates therethrough and a second delay circuit which has a propagation delay of a second delay time when the signal propagates therethrough, and outputs, based on a sum of the first delay time and the second delay time, a detection result indicating the magnitude of noise on power supply voltage applied to the first delay circuit and the second delay circuit. A control unit controls, based on the detection result, a frequency of a clock signal supplied to a circuit unit to which the power supply voltage is applied and the second delay time in such a manner as to exhibit an opposite behavior to a change in the first delay time induced by temperature.