Sampling Clock-Offset Compensation via Threshold Sum Ratios

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Solution Overview

Problem

In digital communication receivers, sampling clock-offsets cause errors in demodulation due to mismatches between desired and actual sampling times, which cannot be resolved by increasing the signal-to-noise ratio (SNR) and result in erroneous symbol decisions.

Innovation Solution

A method that calculates positive and negative thresholds from pulse-shaped data symbols, determining sum ratios to compensate for sampling clock-offsets by shifting the decision window based on these ratios, thereby correcting for clock-offsets without relying on correlation-based techniques.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If correlation-based techniques are used to compensate for sampling clock-offset, then demodulation accuracy can be improved, but computational complexity increases significantly

Engineering Contradiction:
Improvedemodulation accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts only the essential features needed for clock-offset compensation by using simple threshold comparisons of sample sums rather than full correlation computations. This extracts the critical timing information while discarding unnecessary computational overhead, resolving the contradiction between accuracy and complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention uses simple, computationally inexpensive threshold values that can be easily calculated and updated, replacing complex correlation functions. These simple threshold mechanisms provide sufficient compensation accuracy without the heavy computational burden of traditional methods.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Device complexity

If sampling clock-offset is not compensated, then device complexity remains low, but demodulation errors occur due to symbol overlap

Engineering Contradiction:
Improvedevice complexityVSAvoiddemodulation reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent performs preliminary calculations of positive and negative thresholds based on pulse shapes before actual demodulation. This preliminary action prepares the compensation mechanism in advance, enabling simple real-time corrections without adding significant complexity to the main processing path, thus maintaining low device complexity while improving reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention applies partial compensation by adjusting the decision window based on simple sum ratio comparisons rather than attempting perfect alignment. This partial action is sufficient to prevent symbol overlap errors while keeping the compensation mechanism simple and computationally efficient.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9787464B2Method and apparatus for compensating for sampling clock-offset
Publication Date: 2017.10.10 SAMSUNG ELECTRONICS CO LTD
  • US9787464B2 patent drawing
  • US9787464B2 patent drawing
  • US9787464B2 patent drawing

AI summary

A method for compensating for a sampling clock-offset includes calculating a positive threshold and a negative threshold of pulse-shaped data symbols to be received, calculating a positive sum ratio and a negative sum ratio from received samples, and compensating for a sampling clock-offset in response to the positive sum ratio being less than or equal to the positive threshold and the negative sum ratio being less than or equal to the negative threshold.