Clock Synchronization via Offset Tables in Virtualized Systems

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Solution Overview

Problem

As the number of logical domains on an information processing apparatus increases, the frequency of access to the clock device also increases, leading to a higher load on the clock device and bus congestion, which reduces response speed, and poses challenges in maintaining time consistency across multiple clock devices.

Innovation Solution

Implementing a control unit that manages time-of-day differences between physical and logical domains, distributing clock access, and using a service processor to synchronize and maintain time across multiple clock devices, ensuring consistency without continuous correction of clock devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of logical domains implemented on an information processing apparatus is increased, then the processing capacity is improved, but the frequency of access to the clock device increases causing increased load and bus congestion

Engineering Contradiction:
Improveprocessing capacityVSAvoidload on clock device
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the clock access management into segments by introducing a time-of-day offset table that stores individual offset values for each logical domain. This allows each logical domain to be independently managed with its own time offset, enabling parallel access to the clock device without requiring centralized coordination, thereby reducing the load on the clock device while maintaining processing capacity for multiple logical domains.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If the number of clock devices provided in the information processing apparatus is increased, then the load on individual clock devices is reduced, but ensuring consistency in time of day becomes more difficult

Engineering Contradiction:
Improveload on clock deviceVSAvoidtime consistency
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces a time-of-day offset table as an intermediary mechanism that mediates between multiple clock devices and logical domains. The offset table stores and manages time offset values for each logical domain, allowing the system to maintain time consistency across multiple clock devices without requiring them to be continuously synchronized with each other. This intermediary structure enables independent clock devices to serve multiple logical domains while maintaining reliability through centralized offset management.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If continuous correction of clock devices is performed to maintain time consistency, then time accuracy is improved, but processing overhead increases

Engineering Contradiction:
Improvetime accuracyVSAvoidprocessing overhead
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing time-of-day offsets for each logical domain in the offset table before actual time access occurs. When a logical domain needs to access the clock, the system simply retrieves the pre-stored offset value rather than performing continuous correction calculations. This preliminary preparation of offset values maintains time accuracy while significantly reducing the processing overhead during runtime operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP2498163B1Information Processing Apparatus and Time-of-Day Control Method
Publication Date: 2021.03.24 FUJITSU LTD
  • EP2498163B1 patent drawingFigure 1
  • EP2498163B1 patent drawingFigure 2
  • EP2498163B1 patent drawingFigure 3

AI summary

In an information processing apparatus, a control unit includes a first clock device for providing the time of day. A physical domain includes a second clock device, and implements a logical domain that functions as a virtual information processing apparatus. The control unit controls a first time-of-day difference between the time of day of the first clock device and that of the second clock device. The physical domain controls a second time-of-day difference between the time of day of the second clock device and that of the logical domain. In the information processing apparatus, the time of day on the logical domain is controlled based on the first and second time-of-day differences.