Clock Oscillator Control Circuit for Glitch-Free Enable Signals
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Solution Overview
Problem
In large and complex circuit systems, the combination of multiple asynchronous clock request signals can result in unpredictable behavior of the clock oscillator due to short glitches in the composite clock request signal, leading to inefficiencies and potential data errors.
Innovation Solution
A clock oscillator control circuit comprising a signal processor to remove glitches from the composite clock request signal, logic circuitry to generate set and reset signals based on the processed signal and a clock oscillator valid signal, and a set-reset latch to output an enable signal to the clock oscillator, ensuring stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple asynchronous clock request signals are combined in a logical OR circuit, then the clock oscillator can be enabled when any circuit module needs a clock input, but the resulting composite clock request signal may include short glitches that cause the clock oscillator to behave in an unpredictable manner
Solution Approach 1:
The signal processor performs preliminary processing on the composite clock request signal to detect and remove glitches before the signal is used to control the clock oscillator. This preliminary action prevents glitches from causing unpredictable clock oscillator behavior while maintaining the ability to integrate multiple asynchronous clock request signals.
2Use of energy by moving object
If the clock oscillator is enabled only when circuit modules need clock input, then power consumption is reduced, but glitches in the enable signal can cause the clock oscillator to behave unpredictably
Solution Approach 1:
The signal processor acts as an intermediary between the composite clock request signal and the clock oscillator enable signal. It processes the clock request signal to remove glitches while preserving the power-saving enable/disable functionality, thereby mediating between energy efficiency requirements and reliable clock oscillator operation.
3Speed
If asynchronous clock request signals are processed without glitch detection, then the system response time is faster, but the clock oscillator may experience unpredictable behavior due to transient glitches
Solution Approach 1:
The patent replaces simple logical OR circuitry with a more sophisticated signal processing system that uses timing analysis and pattern recognition to distinguish between valid clock requests and glitch artifacts. This substitution maintains fast response times while filtering out harmful glitches through intelligent signal processing rather than simple logic gates.
Data Source
AI summary
A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.