Clock Oscillator Enable Circuit for Glitch-Free Request Handling
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Solution Overview
Problem
In large and complex circuit systems, the combination of multiple asynchronous clock request signals can result in unpredictable behavior of the clock oscillator due to short glitches in the composite clock request signal, leading to instability and potential incorrect data processing.
Innovation Solution
A clock oscillator control circuit comprising a signal processor to remove transient glitches from the composite clock request signal, logic circuitry to generate set and reset signals based on the processed signal and a clock oscillator valid signal, and a set-reset latch to output an enable signal to the clock oscillator, ensuring stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple asynchronous clock request signals are combined in a logical OR circuit, then the clock oscillator can be enabled when any module needs a clock signal, but short glitches may appear in the composite clock request signal causing unpredictable clock oscillator behavior
Solution Approach 1:
The patent applies preliminary action by filtering and conditioning the composite clock request signal before it reaches the clock oscillator. A signal processing circuit detects and removes transient glitches from the OR-combined clock request signals, ensuring that only stable, valid enable signals are transmitted to the clock oscillator. This preprocessing prevents unpredictable clock behavior while maintaining the ability to respond to any module's clock needs.
Solution Approach 2:
The patent introduces an intermediary signal processing circuit between the logical OR combination of clock request signals and the clock oscillator. This intermediary component processes the composite signal, removing harmful transient glitches while preserving the essential enable functionality. The mediator ensures that the clock oscillator receives clean, reliable enable signals without directly exposing it to the raw combined clock requests.
2Loss of energy
If the clock oscillator is disabled when no circuit modules need clock signals, then power consumption is reduced, but the clock oscillator may exhibit unpredictable behavior when re-enabled due to glitch signals
Solution Approach 1:
Before re-enabling the clock oscillator, the signal processing circuit performs preliminary filtering to remove transient glitches from the enable signal. This ensures that when the clock oscillator transitions from disabled to enabled state, it receives a clean, stable signal rather than a glitch-contaminated signal, preventing unpredictable behavior during power-saving mode transitions.
Solution Approach 2:
The patent implements feedback mechanisms where the signal processing circuit continuously monitors the composite clock request signal and dynamically adjusts the enable signal sent to the clock oscillator. By detecting transient conditions and providing feedback control, the system ensures that the clock oscillator is only enabled when the enable signal is stable and free from glitches, maintaining reliability during power management operations.
Data Source
AI summary
A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.