Clock Path Control Circuit for Dynamic Current Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices experience increased dynamic current consumption due to unnecessary toggling of the clock signal, particularly as frequency increases, necessitating a reduction in current consumption.
Innovation Solution
A clock path control circuit is introduced, comprising a clock control signal generating unit that delays the inactivation time of the data input buffer enable signal and generates a clock control signal with an activation period exceeding the buffer's activation period, and a clock transfer unit that provides the clock signal to the write clock path during this extended activation period, thereby controlling the toggling of the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock signal frequency is increased to improve performance, then the processing speed is improved, but the dynamic current consumption is increased
Solution Approach 1:
The patent applies periodic action by controlling the clock signal to toggle only during specific activation periods corresponding to data input buffer operations. The clock control signal generating unit generates control signals that enable the clock transfer unit to pass the clock signal to the write clock path only when needed, creating a periodic toggling pattern rather than continuous toggling. This reduces the average current consumption while maintaining processing speed during active periods.
2Loss of time
If the clock signal is continuously toggled to maintain operational readiness, then the response time is improved, but the current consumption is increased
Solution Approach 1:
The patent implements preliminary action by generating the clock control signal in advance based on the activation period of the data input buffer. The clock control signal generating unit anticipates when the clock signal will be needed and prepares the control signal accordingly, ensuring that the clock signal is ready to toggle immediately when data input operations begin, thus maintaining fast response time without requiring continuous toggling.
3Device complexity
If the clock signal is provided to all clock paths simultaneously, then the system simplicity is maintained, but the current consumption is increased
Solution Approach 1:
The patent applies segmentation by dividing the clock distribution into separate controllable paths. The clock transfer unit acts as a gate that selectively directs the clock signal to the write clock path based on the clock control signal. This segmentation allows different clock paths to be activated independently, reducing the total number of toggling clocks and thereby reducing current consumption while maintaining manageable system complexity through modular control.
Data Source
AI summary
A clock path control circuit includes a clock control signal generating unit configured to generate a clock control signal having an activation period corresponding to an activation period of a data input buffer; and a clock transfer unit configured to provide a clock signal to a write clock path in response to the clock control signal during the activation period of the clock control signal.