Clock Path Circuit for Phase-Synchronized Data Clock Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor apparatuses face challenges in generating internal clock signals synchronized with system clock signals due to asynchronous delays, leading to phase differences, which existing delay-locked loop circuits struggle to fully compensate for, affecting data clock signal generation and reliability.
Innovation Solution
The semiconductor apparatus includes an internal clock generating circuit that generates multiple internal clock signals with different phases, a stop controlling circuit to manage clock levels and stop signals, and a data clock generating circuit that produces data clock signals and their complements based on these internal clock signals and clock level signals, ensuring synchronization and adjusting driving force according to command signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay-locked loop circuit is used to compensate for asynchronous delay, then phase synchronization between internal clock signals and system clock signals is improved, but device complexity increases
Solution Approach 1:
The delay compensation function is segmented into multiple independent delay elements arranged in parallel paths. Each delay element provides a fixed delay amount, and the desired total delay is achieved by selectively enabling combinations of these elements, replacing a complex continuous delay adjustment mechanism with simpler discrete segments.
Solution Approach 2:
The delay amount is made dynamically adjustable through control signals that selectively activate different delay elements. This allows the system to adaptively compensate for varying asynchronous delays under different operating conditions without requiring a complex fixed-delay design, improving phase synchronization while keeping individual delay elements simple.
2Adaptability or versatility
If multiple internal clock signals with different phases are generated, then data clock signal generation flexibility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The required phase differences between internal clock signals are predetermined and built into the delay element design during manufacturing. Each delay element is designed with a fixed, precise delay characteristic, so that when combined in different sequences, they automatically produce the required phase relationships without requiring complex real-time adjustment mechanisms.
Solution Approach 2:
The phase characteristics of internal clock signals are controlled by changing the activation state of different delay elements rather than by continuous parameter adjustment. By selectively enabling or disabling specific delay elements based on control signals, the system achieves flexible phase configuration while relying on the precise, fixed characteristics of each delay element to maintain manufacturing feasibility.
Data Source
AI summary
A semiconductor apparatus includes an internal clock generating circuit, a stop controlling circuit, and a data clock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a clock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.