Clock Path Equalization for Early-Edge Jitter Reduction

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Solution Overview

Problem

High-speed digital communication systems face performance and complexity issues due to the need for clock signals to stabilize after transitioning from an idle state, leading to unacceptable wait times and increased power consumption, particularly in low-power systems.

Innovation Solution

The implementation of a clock equalization system using continuous-time linear equalizers (CTLEs) and digitally controlled delay lines to reduce intersymbol interference (ISI) and jitter, allowing for quicker transition between idle and active states without compromising synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If clock signals are disabled or placed in idle state when not in use, then power consumption is reduced, but the clock signal requires time to stabilize after transitioning from idle state

Engineering Contradiction:

Improvepower consumptionVSAvoidwait time for clock stabilization

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The system performs preliminary equalization of the clock signal path during active operation so that when the clock transitions to idle and back to active state, the signal path is already prepared and stable, eliminating the need for wait time after idle transition

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system uses feedback mechanisms to monitor clock signal quality and dynamically adjust equalization parameters, ensuring the clock signal stabilizes quickly after idle transitions while maintaining power efficiency

Inventive Principle:

Principle #23Feedback

2Reliability

If circuits are designed to ignore early clock edges until clock signal stabilizes, then synchronization reliability is improved, but system complexity and performance are degraded

Engineering Contradiction:

Improvesynchronization reliabilityVSAvoidsystem complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of ignoring early clock edges, the system inverts the approach by actively equalizing and improving the quality of early clock edges, allowing them to be used immediately for synchronization without discarding them

Inventive Principle:

Principle #13The other way round (Inversion)

3Speed

If high-bandwidth clock paths are used to reduce wait time, then transition speed between idle and active states is improved, but power consumption increases

Engineering Contradiction:

Improvetransition speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts equalization parameters based on the clock signal state and transition requirements, providing high-bandwidth equalization only when needed during transitions while maintaining lower power consumption during steady active or idle states

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes equalization parameters dynamically to optimize the balance between transition speed and power consumption, adjusting the degree of equalization based on operational requirements

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8890580B2Methods and circuits for reducing clock jitter

Publication Date: 2014.11.18 RAMBUS INC

AI summary

A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.