Clock Path Circuit with Feedback Delay for Synchronized Data Clocks
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Solution Overview
Problem
Semiconductor apparatuses face phase differences and asynchronous delays in generating internal clock signals, leading to inefficiencies in clock synchronization and data transmission.
Innovation Solution
Incorporating an internal clock generating circuit, a stop controlling circuit, and a data clock generating circuit to produce multiple internal clock signals with varying phases, a stop signal, and clock level signals, which are used to synchronize data clock signals with system clock signals, and adjust driving force based on command signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If internal clock signals are generated through various internal circuits, then multiple clock signals with different phases can be produced, but asynchronous delay occurs leading to phase differences between internal clock signals and system clock signal
Solution Approach 1:
The patent implements a delay-locked loop circuit that uses feedback mechanisms to detect phase differences between internal clock signals and system clock signal, then automatically adjusts delay amounts to synchronize the phases. The circuit monitors the phase relationship and dynamically compensates for asynchronous delays through feedback control.
Solution Approach 2:
The patent changes the delay parameter of the delay element dynamically to adjust the phase of internal clock signals. By varying the delay amount based on detected phase differences, the system achieves synchronization while maintaining the ability to generate multiple phase-diverse clock signals.
2Reliability
If delay-locked loop circuit is used to compensate asynchronous delay, then clock signal phase synchronization can be achieved, but device complexity increases
Solution Approach 1:
The patent segments the delay compensation function into modular components: a delay element with controllable delay amount, a phase detection unit, and a control unit. This modular segmentation allows the complex synchronization function to be implemented through coordinated simple modules rather than a monolithic complex circuit.
Solution Approach 2:
The delay-locked loop circuit is designed to serve multiple functions: generating phase-diverse clock signals, detecting phase differences, compensating asynchronous delays, and synchronizing with the system clock signal. This multi-functionality reduces the need for separate dedicated circuits for each function.
3Productivity
If data clock signal is generated based on internal clock signals, then data transmission can be performed, but phase differences may cause transmission errors
Solution Approach 1:
The patent performs preliminary phase synchronization using the delay-locked loop circuit before generating data clock signals for data transmission. By pre-compensating phase differences and synchronizing internal clock signals with the system clock signal, the system ensures that subsequent data transmission operations occur with properly aligned clock phases, preventing transmission errors.
Data Source
AI summary
A semiconductor apparatus includes an internal dock generating circuit, a stop controlling circuit, and a data dock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a dock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.