Clock Path Jitter Compensation Under Power Supply Variation
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Solution Overview
Problem
Memory devices experience clock jitter due to variations in power supply voltage and current, which affect the synchronization of operations and can lead to time variations in clock signals and outputs, despite operating within specified parameters.
Innovation Solution
The implementation of jitter compensation circuits within the clock path, which modulate delay based on bias currents or voltages to counteract the sensitivity of clock components to power supply variations, and mix clock paths to minimize power supply-induced jitter, ensuring consistent clock signal delivery across varying power levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory devices operate within specified power supply parameters, then proper operation is maintained, but clock jitter still occurs due to component sensitivity to supply variations
Solution Approach 1:
The patent implements a feedback mechanism where the actual power supply voltage is sensed and used to dynamically adjust the clock signal timing. A voltage sensor monitors the power supply voltage, and based on the sensed voltage level, the system compensates for timing variations in the clock path components, thereby maintaining precise clock signal timing despite power supply variations
Solution Approach 2:
The patent changes the timing parameters of clock path components dynamically based on the sensed power supply voltage. By adjusting delay elements and timing characteristics in response to voltage variations, the system compensates for the sensitivity of clock components to power supply changes, maintaining consistent clock signal timing across different operating conditions
2Manufacturing precision
If clock path components are made more sensitive to timing control, then clock signal precision can be improved, but sensitivity to power supply variations increases causing more jitter
Solution Approach 1:
The patent introduces an intermediary voltage sensing and control mechanism between the power supply and the clock path components. This intermediary system monitors the power supply voltage and generates compensating control signals that offset the harmful effects of voltage variations on timing-critical components, thereby reducing their effective sensitivity to power supply fluctuations while maintaining timing precision
3Reliability
If multiple clock paths are used to distribute clocks throughout the memory device, then synchronization coverage is improved, but variations in supply voltage cause different jitter levels across paths
Solution Approach 1:
The patent applies local quality by implementing individual voltage sensing and compensation mechanisms for different clock path regions. Each clock path or region receives tailored timing adjustments based on its local power supply conditions, allowing the system to maintain consistent timing precision across multiple distributed clock paths despite varying local voltage conditions
Data Source
AI summary
Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response.