Clock Path Jitter Analysis Using STA and Voltage Drop Extremes
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Solution Overview
Problem
Conventional clock jitter analysis methods are time-consuming and limited to analog circuits, failing to accurately identify potential timing issues in integrated circuits, especially when analog and digital circuits are integrated, leading to increased risks of off-gauge circuits.
Innovation Solution
An electronic device and method that utilize a storage device and processing device to perform static timing analysis on clock paths, calculating maximum and minimum voltage drops to obtain timing reports, and determining clock jitter based on time differences between these reports, enabling fast and accurate clock jitter analysis applicable to both analog and digital circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dynamic simulation is used for clock jitter analysis, then analysis accuracy is improved, but analysis time and operation resources are excessively consumed
Solution Approach 1:
The patent uses a simplified STA-based analysis method instead of complex dynamic simulation, creating a lightweight analysis approach that consumes minimal resources while providing sufficient accuracy for clock jitter analysis in mixed-signal circuits
Solution Approach 2:
The patent changes the analysis parameters by using voltage drop extremes (maximum and minimum voltage drops) in STA to represent clock jitter effects, transforming a dynamic simulation problem into a static analysis problem with varied parameters
2Measurement precision
If transistor level circuit simulation is used, then detailed timing analysis is achieved, but large digital circuits cannot be simulated and can only be roughly estimated
Solution Approach 1:
The patent creates a universal STA-based methodology that works for both analog and digital circuits in mixed-signal designs, making the analysis tool versatile across different circuit types without requiring separate analysis methods
Solution Approach 2:
The patent segments the clock tree into multiple clock paths and performs STA on each path separately using voltage drop information, enabling analysis of large digital circuits by breaking them into manageable segments
3Reliability
If conventional dynamic simulation is used for mixed-signal circuits, then comprehensive timing problems can be identified, but analysis time is too long and operation costs are high
Solution Approach 1:
The patent performs preliminary STA with extreme voltage drop values to predict clock jitter effects before final verification, enabling early identification of timing problems in mixed-signal circuits without requiring lengthy dynamic simulations
Solution Approach 2:
The patent introduces voltage drop information as an intermediary parameter that bridges the gap between power analysis and timing analysis, enabling STA to capture clock jitter effects without requiring full dynamic simulation
Data Source
AI summary
An electronic device and a clock jitter analysis method are provided. The electronic device includes a storage device and a processing device. The processing device is configured to: read timing simulation information and voltage drop information of a plurality of clock paths from the storage device; obtain a maximum voltage drop and a minimum voltage drop of each clock path based on the voltage drop information; perform a first static timing analysis (STA) with the maximum voltage drop based on the timing simulation information, to obtain a first timing report; perform a second STA with the minimum voltage drop based on the timing simulation information, to obtain a second timing report; calculate time information corresponding to each clock path based on the first timing report and the second timing report; and select largest time information of the plurality of pieces of time information as a clock jitter.