Semiconductor Clock Path Selection With Phase-Detector Alignment
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Solution Overview
Problem
Conventional semiconductor devices face challenges in aligning multiple clock signals, particularly in next-generation memories like GDDR5, which use differential command and write clocks, requiring further synchronization to enhance system performance.
Innovation Solution
A semiconductor device with a selection circuit and phase detector that generates a voltage signal indicating phase differences between clock signals, allowing the controller to align the phases of input/output clock signals, including a serializer to output serialized data and a phase aligner to optimize clock synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple different clock signals (CK and WCK) are used in next-generation memories, then system performance is improved, but clock synchronization and alignment become more complex
Solution Approach 1:
A phase detector is introduced as an intermediary component to measure and compare the phase differences between multiple clock signals (CK and WCK). The phase detector generates voltage signals that indicate phase relationships, enabling the controller to automatically adjust and synchronize the clocks without complex manual configuration, thus resolving the synchronization complexity while maintaining high performance
Solution Approach 2:
The patent implements a feedback mechanism where the phase detector continuously monitors clock phase differences and feeds back voltage signals to the controller. The controller uses this feedback to dynamically adjust the timing and alignment of clock signals, ensuring synchronized operation of multiple clocks throughout system operation, which simplifies the management of complex multi-clock systems
2Measurement precision
If phase alignment of multiple clock signals is implemented, then data output timing accuracy is improved, but additional circuit components are required
Solution Approach 1:
The phase detector serves as an intermediary that precisely measures phase differences between clock signals and converts them into usable voltage signals. This intermediary component enables accurate timing measurement without requiring complex direct comparison circuits, achieving high timing precision while adding minimal circuit complexity
Solution Approach 2:
The patent replaces mechanical or manual timing adjustment mechanisms with an electronic phase detection and voltage signal-based control system. This substitution enables automated, precise timing alignment through electrical signals rather than physical adjustments, improving timing accuracy while reducing the need for complex manual intervention circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves clock synchronization, reducing data output timing errors and enhancing system performance by aligning multiple clock signals effectively, even in systems with varying clock characteristics and feedback path delays.
Implementation Method 1
a phase detector to generate a voltage signal indicating a phase difference between a second clock signal output from the controller and the timing signal output from the selection circuit
Data Source
AI summary
A semiconductor device includes a selection circuit and a phase detector. The selection circuit, in response to a first selection signal output from a controller, outputs as a timing signal a first clock signal output from the controller or an output signal of a PLL using the first clock signal as a first input. The phase detector generates a voltage signal indicating a phase difference between a second clock signal output from the controller and the timing signal output from the selection circuit. The semiconductor device further includes a data port, a memory core storing data, and a serializer, in response to the timing signal output from the selection circuit, serializing the data output from the memory core and outputting serialized data to the controller via the data port. The first selection signal is generated by the controller based on at least one of the voltage signal and the data output to the controller via the data port.