Clock Path Switching Circuit for Stable Internal Voltage
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Solution Overview
Problem
Existing semiconductor devices face reliability issues due to undesired transitions and phase shifts in clock signals when switching between slow and fast clock speeds, leading to excessive internal voltage variations that can cause electrical stress to components and disrupt delay-locked loop operations.
Innovation Solution
Synchronizing the control signal with the incoming edge of an input clock signal to align transitions, using additional flip-flops and logic gates to ensure that clock speed changes occur predictably and within specifications, preventing unwanted phase shifts and voltage excursions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock speed switching is implemented to improve performance and power savings, then device functionality and energy efficiency are improved, but internal voltage variations increase causing electrical stress and reliability issues
Solution Approach 1:
The patent applies preliminary action by synchronizing the clock speed switching event with the next incoming edge of the input clock signal. This advance alignment ensures that transitions occur at predetermined safe moments, preventing unwanted phase shifts and voltage excursions before they can cause harm to the system
2Adaptability or versatility
If asynchronous control signals are used for clock speed switching, then switching flexibility is improved, but unwanted phase shifts and additional charge pumping cycles occur
Solution Approach 1:
The patent employs feedback by monitoring the input clock signal edges and using this information to determine the precise timing for clock speed switching. The switching decision is based on feedback from the clock signal's current state, ensuring transitions occur only at appropriate moments when no harmful phase shifts will result
3Speed
If internal voltage is increased during fast clock operation, then clock speed performance is improved, but electrical stress on components increases
Solution Approach 1:
The patent applies preliminary anti-action by preventing voltage excursions before they can occur. By synchronizing clock speed transitions with incoming clock edges, the system proactively avoids the conditions that would generate harmful voltage variations and electrical stress on components
Data Source
AI summary
Techniques for reliable clock speed change and associated circuits and methods are disclosed. Internal voltage supplies of semiconductor devices may include oscillators and charge pump circuits. The oscillator may include at least two clock paths for generating clock signals having different clock frequencies, which can be provided to the charge pump circuit. Further, the oscillator may generate a reset signal configured to activate one clock path over the other (e.g., changing clock speeds). In some embodiments, the oscillator includes a flip-flop to align the reset signal with respect to an edge of an input clock signal supplied to the oscillator such that unintentional (undesired, unexpected) features in the output signal of the oscillator can be avoided when the oscillator changes clock speeds.