Pattern-Selected Clock Generation for Low-Jitter Phase Alignment
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Solution Overview
Problem
High-speed and complex circuits face challenges in phase-aligning multiple clock signals, leading to issues with skew, jitter, and noise, making it difficult to maintain synchronization and stability, especially when using phase-locked loop systems.
Innovation Solution
A clock signal generator system that uses a pattern selector and pattern generator to create phase-aligned clock signals by determining the structure of the generated clock signals based on input signal patterns, ensuring consistent skew and synchronization across multiple clock signals derived from a common reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clock root signals are phase-aligned using traditional PLL systems, then clock synchronization is achieved, but skew, jitter, and noise increase
Solution Approach 1:
The patent segments the clock signal generation by creating multiple independent clock root signals from separate PLL systems, each generating its own phase-aligned clock signals. This segmentation allows each PLL to operate independently with optimized parameters, reducing the accumulation of skew and jitter that occurs when multiple clock roots are forced to align through a single centralized system.
Solution Approach 2:
The patent changes the parameters of each PLL system to optimize clock signal generation for specific frequency ratios and phase alignment requirements. By adjusting PLL parameters such as reference frequencies, division ratios, and phase offset values, the system achieves precise phase alignment between clock root signals while minimizing skew, jitter, and noise through parameter optimization rather than structural complexity.
2Adaptability or versatility
If the number of clock root signals increases, then more clock signals can be generated, but stability and predictability decrease
Solution Approach 1:
The patent divides the clock signal generation into multiple independent segments, where each PLL system generates a specific number of phase-aligned clock root signals. This segmentation isolates the stability requirements of each clock root generation, preventing the degradation that would occur if all clock roots were generated in a single interconnected system. Each segment maintains its own stability independently.
Solution Approach 2:
The patent establishes equipotentiality by ensuring that all clock root signals within each PLL system maintain equal phase relationships and timing characteristics. By creating phase-aligned clock roots with consistent skew, jitter, and noise parameters across multiple PLL systems, the system maintains stability and predictability even as the total number of clock signals increases.
3Reliability
If clock dividers are merged into the PLL system design, then phase alignment is improved, but design complexity and verification difficulty increase
Solution Approach 1:
The patent segments the clock signal generation architecture into distinct PLL systems that each handle specific phase alignment requirements. Rather than merging all clock dividers into a single complex PLL system, the patent creates multiple independent PLL units, each responsible for generating phase-aligned clock roots for specific frequency ratios. This segmentation reduces design complexity and verification difficulty while maintaining phase alignment through modular design.
4Reliability
If cascaded multiplexer circuits are used to generate clock root signals, then phase alignment is achieved, but signal path length increases causing high jitter
Solution Approach 1:
The patent extracts the phase alignment function from the clock divider circuits and integrates it directly into the PLL system design. By taking out the phase alignment requirement and implementing it at the PLL level through phase-offset controlled clock signal generation, the patent eliminates the need for cascaded multiplexer circuits. This extraction approach maintains phase alignment while significantly reducing signal path length and the associated jitter.
Data Source
AI summary
A apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.