Clock Signal Generation by Quotient-Remainder Period Distribution
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Solution Overview
Problem
Conventional frequency synthesizers require large capacitors to change low-frequency input signals into output signals, which is not integratable with semiconductor technology and results in long phase-locking times when using digital phase locked loops.
Innovation Solution
A clock signal generating circuit that includes a counter, clock signal generator, divider, pulse signal generator, modulator, delay unit, and selector to divide the input clock signal into a quotient and remainder, setting the quotient as the reference period and distributing the remainder across multiple periods of the output clock signal, allowing for frequency change without increasing capacitor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large capacitor is used in the loop filter to change low-frequency input signals into output signals, then the frequency conversion capability is improved, but the device size and integration difficulty increase
Solution Approach 1:
The patent replaces the conventional analog loop filter capacitor with a digital signal processing approach. The frequency synthesis function is achieved through digital division and modulation operations in the frequency domain, eliminating the need for large physical capacitors while maintaining the ability to convert low-frequency input signals to desired output frequencies.
Solution Approach 2:
The invention changes the operating parameters from time-domain analog filtering to frequency-domain digital processing. By performing division operations on the input signal frequency and using modular arithmetic to generate output frequencies, the system achieves flexible frequency conversion without being constrained by capacitor size limitations.
2Ease of manufacture
If a digital phase locked loop is used to avoid large capacitors, then the device integration is improved, but the phase-locking time increases significantly
Solution Approach 1:
The patent performs preliminary frequency division and remainder calculation operations before generating the output clock signal. By pre-computing the quotient and remainder of the division operation and using these to directly control the output frequency, the system achieves rapid frequency locking without requiring multiple input signal periods, thus reducing phase-locking time while maintaining digital integration advantages.
3Ease of manufacture
If the capacitor size is reduced for semiconductor integration, then the manufacturability is improved, but the frequency conversion capability for low-frequency inputs deteriorates
Solution Approach 1:
The patent substitutes the physical capacitor-based frequency filtering mechanism with digital signal processing operations. The frequency conversion capability is maintained through mathematical operations (division, modulo) performed on the input signal characteristics, allowing small integrated circuits to achieve the same functionality that previously required large discrete capacitors.
Solution Approach 2:
The invention creates a universal frequency synthesis approach that can handle various input frequencies without requiring different hardware components. The digital processing architecture provides multi-functionality, enabling the same circuit to convert different low-frequency inputs to desired output frequencies, thereby maintaining adaptability while achieving semiconductor integration.
Data Source
AI summary
The present invention relates to a clock signal generating circuit and a power supply including the same. The present invention includes: a counter for counting one period of an input clock signal by using a reference clock signal, and generating a count signal; and a clock signal generator for receiving the count signal and the reference clock signal, dividing the count signal to generate a quotient and a remainder, setting the quotient as a reference period of an output clock signal, and distributing and disposing the remainder to the output clock signal with a plurality of periods occurring for one period of the input clock signal.