Per-Instruction Clock Period Synthesis for Fine-Grain Power Control
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Solution Overview
Problem
Existing clock frequency manipulation methods in processors lack sufficient granularity and responsiveness, leading to inefficiencies in system performance optimization, particularly in high-speed processors with varying computational modes, and incur substantial implementation and operational costs.
Innovation Solution
Implement clock period synthesis (CPS) methods that dynamically adjust the clock period on a per-instruction basis using a fully-decoded high-speed shift register, enabling precise control of clock waveforms and reducing power consumption through optimized duty cycles and current changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional clock frequency manipulation methods are used, then the system can operate at fixed frequencies, but the granularity and responsiveness for optimizing system performance metrics are insufficient
Solution Approach 1:
The patent implements dynamic clock period adjustment by replacing fixed-frequency clock generators with a mechanism that continuously varies clock periods based on real-time computational requirements. The clock period is dynamically synthesized using a formula that incorporates current computational workload, target frequency, and duty cycle parameters, enabling the system to adapt clock timing to match actual processing needs rather than operating at static frequencies.
Solution Approach 2:
The patent changes multiple clock parameters simultaneously including period, frequency, and duty cycle to optimize system performance. By modifying the clock period synthesis formula to include duty cycle as a variable parameter and adjusting frequency based on computational metrics, the system achieves fine-grained control over clock characteristics without requiring complex separate control mechanisms for each parameter.
2Adaptability or versatility
If clock frequency is dynamically changed to optimize performance, then system responsiveness improves, but implementation and operational costs increase substantially
Solution Approach 1:
The patent applies partial action by adjusting clock parameters only to the extent necessary for optimizing performance rather than making extreme changes. The clock period synthesis formula calculates minimal adjustments to frequency and duty cycle based on current computational metrics, avoiding excessive clock changes that would waste energy. This approach achieves adaptability while maintaining energy efficiency by making precisely-sized parameter adjustments.
Solution Approach 2:
The patent implements feedback control by continuously monitoring computational activity levels and using this information to adjust clock parameters. The system measures actual performance metrics and feeds this information back to the clock synthesis mechanism, which then modifies frequency and duty cycle accordingly. This closed-loop approach ensures clock adaptability matches actual system needs, preventing unnecessary parameter changes that would increase power consumption.
3Speed
If PLL techniques are used for clock frequency synthesis, then frequency control is achieved, but the switchover mechanism causes waveform integrity issues and requires several clock cycles to switch frequencies
Solution Approach 1:
The patent applies preliminary action by pre-calculating the synthesized clock period using a comprehensive formula that accounts for current frequency, target frequency, and duty cycle requirements before actual clock switching occurs. This pre-computation ensures that frequency transitions are planned in advance, maintaining waveform integrity and reducing switching time compared to reactive PLL adjustments that must respond to frequency changes after they are detected.
Solution Approach 2:
The patent substitutes the mechanical PLL locking mechanism with a mathematical clock period synthesis approach. Instead of relying on the physical PLL system to mechanically lock onto new reference conditions (which causes indeterminate waveforms and delays), the system uses a synthesis formula to directly calculate the new clock period, eliminating the mechanical locking process and its associated waveform integrity issues and switching delays.
4Measurement precision
If clock frequency is set to a particular value during execution of an entire algorithm, then frequency stability is maintained, but the granularity for optimizing performance metrics is insufficient
Solution Approach 1:
The patent segments the algorithm execution into multiple phases with different clock period requirements. Instead of maintaining a single fixed clock frequency throughout the entire algorithm, the system divides execution into segments where clock parameters are optimized for each specific phase's computational characteristics. This segmentation enables precise performance optimization for each segment while maintaining overall algorithm stability, reducing total execution time compared to uniform frequency operation.
Solution Approach 2:
The patent implements dynamic clock period adjustment during algorithm execution by continuously synthesizing clock parameters based on current computational state. The clock period synthesis formula is evaluated at different execution points to generate frequency and duty cycle values optimized for each moment's computational requirements, providing fine-grained performance optimization precision without sacrificing algorithm execution stability.
Data Source
AI summary
Clock period synthesis for fine-grain power management is provided. Methods are described for enabling clock waveform synthesis for, in some embodiments, tensor or graphical processors that enable shorter runtime latency, higher computational job throughput, more efficient power management, and a lower implementation cost than alternative clock waveform methods. This Abstract and the independent Claims are concise signifiers of embodiments of the claimed inventions. The Abstract does not limit the scope of the claimed inventions.