Clock Generator Phase Adjustment Without Domain-Wide Restart
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Solution Overview
Problem
Conventional JESD204B/C systems require all clocks in a clock domain to be stopped and restarted for dynamic phase adjustment of one device clock, leading to reduced system performance, utilization, and efficiency.
Innovation Solution
A clock generator circuit with an integer divider, digital delay stage, and analog delay stage, along with math engine circuitry, allows for dynamic phase adjustment of output clocks without resetting other clocks in the domain, using a phase adjustment code comprising integer, fractional cycle, and fine adjustment components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional JESD204B/C systems perform dynamic phase adjustment of one device clock, then phase accuracy is improved, but all other clocks in the domain must be stopped and restarted, reducing system performance and efficiency
Solution Approach 1:
The clock domain is segmented into independent clock generator circuits, each capable of autonomous phase adjustment. The patent divides the monolithic clock domain into multiple independent clock generators (204a, 204b, 204c, 204d), allowing individual phase adjustment without affecting others, thus resolving the contradiction between phase accuracy and system efficiency
Solution Approach 2:
The system implements dynamic phase adjustment capability where each clock generator can independently modify its phase in real-time without requiring system-wide restarts. The phase adjustment words and delay stages enable continuous, dynamic phase control while maintaining operational clocks throughout the domain
2Measurement precision
If dynamic phase adjustment is applied to a system reference clock, then phase offset accuracy is improved, but all system reference modules must be shut down and resynchronized, reducing system utilization
Solution Approach 1:
System reference modules are segmented into independent clock generators, each with autonomous phase control. This allows phase offset adjustment in one module without shutting down others, eliminating system-wide downtime and maintaining continuous operation across the clock domain
Solution Approach 2:
Delay stages and phase adjustment circuits act as intermediaries that enable phase offset application without requiring shutdown. These intermediary components buffer and adjust phases dynamically, allowing continuous operation while achieving accurate phase offset correction
3Stability of the object's composition
If conventional clock systems restart all clocks for phase adjustment, then phase synchronization is improved, but timing interruptions increase, affecting system performance
Solution Approach 1:
The system transitions from static, all-or-nothing phase adjustment to dynamic, selective phase adjustment. Each clock generator can independently adjust its phase in real-time using delay stages and phase adjustment words, maintaining continuous clock operation and eliminating timing interruptions while achieving phase synchronization
Solution Approach 2:
Phase adjustment is achieved by changing delay parameters and divide ratios in individual clock generators rather than restarting clocks. The math engine circuitry computes new phase adjustment codes that modify timing parameters dynamically, maintaining synchronization without causing timing interruptions
Data Source
AI summary
A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.