Clock Phase Alignment Using Fixed Delay Selection for DDR Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed circuit interfaces face challenges in clock alignment due to significant skewing at higher frequencies, which existing physical design approaches and Phase-locked loops (PLLs) fail to adequately address, particularly in System on a Chip (SOC) packages, where these solutions consume more power and space.
Innovation Solution
A clock alignment apparatus and method that samples the phase of a first clock, selectively delays a second clock using a delay circuit, and sets a fixed timing using a logic circuit to match the phases, eliminating the need for PLLs and reducing power consumption and space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Phase-locked loops (PLLs) are used to de-skew clocks in high-speed circuits, then clock alignment is improved, but chip area and power consumption increase
Solution Approach 1:
The patent extracts the essential function of PLL (clock phase alignment) and implements it using a simplified delay circuit that selectively delays the second clock based on sampled phase information. This removes the complex PLL architecture while retaining the core functionality of clock de-skewing, thereby reducing chip area while maintaining clock alignment capability.
Solution Approach 2:
The patent uses a phase detector to sample and capture the phase information of the first clock, creating a digital representation of the phase relationship. This copied phase information is then used to control the delay circuit, replacing the need for complex analog PLL circuits with a simpler digital-controlled approach that consumes less power and occupies less area.
2Reliability
If Phase-locked loops (PLLs) are used to de-skew clocks in high-speed circuits, then clock alignment is improved, but power consumption increases
Solution Approach 1:
The patent extracts the essential function of PLL (clock phase alignment) and implements it using a simplified delay circuit that selectively delays the second clock based on sampled phase information. This removes the complex PLL architecture while retaining the core functionality of clock de-skewing, thereby reducing chip area while maintaining clock alignment capability.
Solution Approach 2:
The patent uses a phase detector to sample and capture the phase information of the first clock, creating a digital representation of the phase relationship. This copied phase information is then used to control the delay circuit, replacing the need for complex analog PLL circuits with a simpler digital-controlled approach that consumes less power and occupies less area.
3Reliability
If physical design approaches are used to align clock signals at lower frequencies, then clock alignment is achieved, but the approach becomes ineffective at higher frequencies where skewing is significant
Solution Approach 1:
The patent implements a dynamic clock alignment solution where the delay circuit can be selectively adjusted based on the actual phase difference between clocks. Unlike static physical design approaches, this system dynamically adapts to frequency changes and skew variations by sampling phase information and adjusting delay accordingly, making it effective across a wide frequency range including high-speed operations.
Solution Approach 2:
The patent changes the delay parameter of the second clock based on sampled phase information from the first clock. This dynamic parameter adjustment allows the system to adapt to different frequency conditions and skew levels, overcoming the limitation of fixed physical design approaches that only work at lower frequencies with minimal skew.
Data Source
AI summary
Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.