Clock Generator Phase Alignment for Large-Difference Clock Interpolation
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Solution Overview
Problem
Conventional phase interpolators are unable to synthesize clocks with a large phase difference, particularly when the clocks are low-frequency, as the transition periods do not overlap, preventing effective phase interpolation.
Innovation Solution
A phase interpolator design incorporating a first delay line with an adjustable delay value based on a delay control code, a delay control circuit for phase comparison, and a second delay line with a delay value corresponding to half of the first delay line's value, allowing for the generation of a middle phase clock between clocks with a large phase difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional phase interpolator is used, then phase interpolation works for small phase differences, but it cannot synthesize clocks with large phase differences when clocks are low-frequency
Solution Approach 1:
The phase interpolation process is segmented into multiple stages: first aligning phases using delay lines, then synthesizing clocks using D-flip flops. This segmentation allows the system to handle large phase differences by breaking down the complex synthesis task into manageable steps, thereby expanding the adaptability to different phase difference ranges while maintaining reliable synthesis capability.
Solution Approach 2:
The invention performs preliminary phase alignment using delay lines before the actual clock synthesis process. By pre-aligning the phases of input clocks, the system ensures that subsequent synthesis operations can successfully combine clocks even when they have large phase differences, thus resolving the contradiction between handling large phase differences and maintaining synthesis reliability.
2Adaptability or versatility
If delay values are adjusted to align phases of clocks with large phase difference, then middle phase clock can be generated, but delay control complexity increases
Solution Approach 1:
The delay lines are designed with dynamically adjustable delay values controlled by control signals. This dynamic adjustment capability allows the system to adaptively align phases of input clocks with different phase differences, achieving phase alignment capability while keeping the control mechanism flexible and manageable through systematic control signal generation.
3Reliability
If transition periods of clocks are made to overlap, then effective phase interpolation is possible, but it requires specific frequency conditions that low-frequency clocks cannot meet
Solution Approach 1:
The system performs preliminary phase alignment using delay lines before attempting synthesis. This preliminary action ensures that the transition periods of aligned clocks will overlap during the synthesis process, guaranteeing effective interpolation regardless of the input clock frequency, thus expanding the frequency range adaptability while maintaining interpolation reliability.
Data Source
AI summary
A clock generator circuit includes: first to Nth nodes, where N is an even number equal to or greater than 2; and a parallel-to-serial conversion circuit suitable for parallel-to-serial converting signals of the first to Nth nodes to output a clock through an output node, wherein, in an activation section of the clock, the signals of even-numbered nodes among the first to Nth nodes have a first level, and the signals of odd-numbered nodes among the first to Nth nodes have a second level which is different from the first level, and wherein, in a deactivation section of the clock, the signals of the first to Nth nodes have the same level.