Digital Clock Phase Alignment Circuit for Jitter-Stable Operation
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Solution Overview
Problem
Clocking in integrated circuits, particularly in space applications, is prone to interruptions due to single event upsets and environmental conditions, leading to undesirable results.
Innovation Solution
A phase alignment circuit comprising a frequency adjuster, phase adjuster, and XOR gate that aligns digital clock signals by receiving multiple copies of an input clock signal, confirming phase alignment through an XOR function, and generating phase-aligned clock signals for the integrated circuit, allowing for frequency adjustment and phase locking to ensure continuous operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple copies of clock signals are distributed to different parts of an integrated circuit, then the circuit can operate in parallel with improved productivity, but phase misalignment and jitter increase leading to reduced reliability
Solution Approach 1:
The patent divides the clock distribution system into multiple independent phase alignment circuits, each handling specific clock signal copies. This segmentation allows parallel processing of clock signals while maintaining individual phase control, resolving the contradiction between parallel operation capability and clock signal stability.
Solution Approach 2:
The patent implements feedback mechanisms where phase alignment circuits continuously monitor clock signal phases and automatically adjust timing deviations. This closed-loop feedback system maintains phase coherence across multiple clock copies, enabling reliable parallel operation despite signal distribution variations.
2Reliability
If phase alignment circuits are added to maintain clock signal coherence, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent uses simplified copy-based phase alignment circuits that replicate proven design patterns. By copying and standardizing the phase alignment logic across multiple instances, the patent achieves reliable phase coherence while controlling overall system complexity through reuse of verified circuit blocks.
3Manufacturing precision
If frequency adjustment and phase locking are implemented to align clock signals, then phase alignment is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs parameter-adjustable phase alignment circuits that can be configured through standard design parameters rather than requiring precise physical fabrication tolerances. By making phase alignment behavior controllable through electrical parameters rather than manufacturing tolerances, the patent achieves high phase alignment accuracy while maintaining ease of manufacture.
Data Source
AI summary
A method and apparatus for aligning the phases of digital clock signals are disclosed. For example, a phase alignment circuit according to one embodiment includes a frequency adjuster comprising a first plurality of inputs, where at least some of the first plurality of inputs are coupled to an output of a digital clock of an integrated circuit, a phase adjuster comprising a second plurality of inputs, where at least some of the second plurality of inputs are coupled to a plurality of outputs of the frequency adjuster, and an XOR gate comprising a third plurality of inputs, each of the third plurality of inputs being coupled to one of the plurality of outputs of the frequency adjuster.