Clock Signal Phase Difference Calibration Without Service Loss

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Solution Overview

Problem

Existing methods for determining phase differences between clock signals in electronic components are complex, costly, and prone to service loss during calibration, especially when dealing with high channel counts, and do not account for component aging.

Innovation Solution

A method involving the transmission of calibration signals between electronic components to measure phase differences using synchronized clock signals, with steps to determine the number of clock pulses between active edges to calculate phase differences, allowing real-time adjustments without service loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If calibration channels are added to measure phase difference in real time, then phase measurement capability is improved, but device complexity and size increase

Engineering Contradiction:
Improvephase difference measurementVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent makes existing data channels perform dual functions: they continue to transmit normal data traffic while simultaneously serving as calibration channels for phase difference measurement. This eliminates the need for dedicated calibration channels and switches, reducing device complexity while maintaining real-time phase measurement capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system uses its own existing infrastructure (data channels) to perform calibration functions, rather than requiring external or dedicated calibration resources. The data channels themselves provide the measurement capability needed for phase difference determination

Inventive Principle:
Principle #25Self-service

2Measurement precision

If calibration mode is implemented, then phase difference measurement is improved, but service continuity deteriorates due to mode switching

Engineering Contradiction:
Improvephase difference measurementVSAvoidservice continuity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent enables phase difference measurement to occur continuously in the background during normal data transmission without requiring mode switching. The calibration function operates concurrently with data transmission, eliminating service interruptions while maintaining continuous phase measurement capability

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The system performs phase difference measurements periodically using embedded calibration sequences within the normal data stream, allowing continuous operation while maintaining updated phase information without interrupting service

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If correlation-based phase difference measurement is used, then measurement accuracy is improved, but computing power requirements increase

Engineering Contradiction:
Improvephase difference measurementVSAvoidcomputing power
Core Design Contradiction:
Measurement precisionVSPower

Solution Approach 1:

The patent extracts the phase difference measurement function from the main data processing path and implements it as a separate, optimized calibration routine. This separates the measurement computation from general data processing, allowing for more efficient resource allocation and reduced overall computing power requirements

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12425011B2Method for determining the phase difference between a first clock signal received by a first electronic component and a second clock signal received by a second electronic component
Publication Date: 2025.09.23 TELEDYNE E2V SEMICON SAS
  • US12425011B2 patent drawing
  • US12425011B2 patent drawing
  • US12425011B2 patent drawing

AI summary

The invention relates to a method for determining the phase difference between a first clock signal (CK1) received by a first electronic component (CE1) and a second clock signal (CK2) received by a second electronic component (CE2), comprising the steps of:S10) transmitting a first calibration signal (S12);S20) measuring a first delay (T1);S30) transmitting a second calibration signal (S21);S40) measuring a second delay (T2);S50) measuring the number (n) of clock pulses between the transmission of the first calibration signal (S12) and the active edge of the first clock signal (CK1) consecutive to the active edge of the second calibration signal (S21);S60) determining the phase difference depending on the parity of the number (n) of clock pulses.