Clock Phase Difference Estimation Using Delayed Correlation Sampling

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Solution Overview

Problem

Conventional techniques for signal phase difference estimation lack sufficient resolution for applications involving spatially-distributed sensors, signal-source location systems, and radar-warning receiver systems, necessitating the development of high-resolution methods for accurate phase difference determination.

Innovation Solution

A system and method that include a phase difference estimator configured to iteratively adjust a reference clock signal, sample a monitored clock signal, and correlate noise-reduced samples with a step function to estimate phase differences within a fraction of the symbol period, accounting for propagation delays and noise reduction, enabling precise phase alignment between spatially-distributed components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional techniques are used for signal phase difference estimation, then the system is simple and easy to implement, but the measurement precision is insufficient for high-resolution applications

Engineering Contradiction:
Improvephase difference estimation resolutionVSAvoidestimation system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The phase difference estimation process is segmented into multiple discrete steps: generating test signals with known phase differences, comparing received signals against these test signals, and iteratively refining the estimate. This segmentation allows complex high-resolution estimation to be achieved through a structured sequence of simpler operations, resolving the contradiction between precision and complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by generating test signals with predetermined phase differences before actual measurement. This preparatory step creates a reference framework that simplifies the subsequent measurement process, enabling high-resolution estimation without requiring equally complex real-time processing.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If high-resolution phase difference estimation is implemented, then the measurement precision improves, but the computational complexity and processing time increase

Engineering Contradiction:
Improvephase difference estimation resolutionVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The estimation method employs periodic action through iterative cycles of test signal generation, comparison, and refinement. Each iteration progressively improves precision while the periodic structure allows for optimized processing at each stage, preventing exponential time complexity growth despite high resolution requirements.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system applies partial action by performing comparisons with a finite set of test signals at discrete phase intervals rather than continuous analysis. This approach achieves sufficient precision for practical applications without the excessive computational burden of exhaustive continuous measurement, balancing precision and processing time.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10495727B2Phase difference estimator and method for estimating a phase difference between signals
Publication Date: 2019.12.03 RAYTHEON CO
  • US10495727B2 patent drawing
  • US10495727B2 patent drawing
  • US10495727B2 patent drawing

AI summary

Embodiments of a phase difference estimator and method are generally described herein. The phase difference estimator includes a delay element to delay a reference clock signal that includes an alternating symbol waveform by one of a plurality of delay values. The phase difference estimator further includes a sampler to sample a monitored clock signal provided by a second device responsive to edges of the delayed reference clock signal to generate a sampled signal output. The phase difference estimator further includes a correlation element to correlate the sampled signal output of the sampler with a step function to generate a correlation value for each delay value, and a controller to instruct the delay element to delay the reference clock signal by one of the delay values and provide a phase difference estimate output indicative of a phase difference between the reference and monitored clock signals based on the correlation value.