Clock Phase Calibration Circuit for Multi-Clock Data Interfaces
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Solution Overview
Problem
In systems on-chip (SoCs) with multiple subsystems operating on different clock signals, unknown phase differences between these signals can lead to communication delays and failures due to misalignment of clock cycles, making reliable data transmission challenging.
Innovation Solution
An integrated circuit design that generates multiple phase signals with varying phase offsets relative to a primary clock signal, allowing a phase selector to determine a desirable phase offset for data transmission, ensuring synchronization with the receiving subsystem's clock signal to prevent setup failures and ensure data is processed within the correct clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data transmission is performed between subsystems operating on different clock signals without phase calibration, then the communication process is simple, but the reliability of data reception deteriorates due to unknown phase differences causing setup failures
Solution Approach 1:
The patent changes the phase parameter of clock signals by generating multiple phase-shifted versions of the first clock signal (e.g., 0°, 90°, 180°, 270° phases). The phase selector circuit then selects the appropriate phase parameter that aligns with the second clock signal, resolving the phase mismatch issue and improving data reception reliability without requiring complex external calibration mechanisms
Solution Approach 2:
The phase calibration function is integrated self-service within the first subsystem's output circuitry. The phase selector circuit automatically determines the optimal phase alignment by monitoring setup failures and selecting from pre-generated phase-shifted clock signals, eliminating the need for external phase calibration equipment or complex bidirectional communication protocols
2Reliability
If multiple phase signals are generated and compared to determine optimal phase alignment, then data transmission reliability improves, but the device complexity increases due to additional phase selector circuitry
Solution Approach 1:
The patent segments the clock signal generation function by creating multiple independent phase-shifted clock signals from the original first clock signal. Each phase signal is generated independently with a fixed phase offset, allowing the phase selector circuit to choose the optimal segment (phase) without requiring complex real-time phase adjustment mechanisms
Solution Approach 2:
The patent performs preliminary action by pre-generating multiple phase-shifted clock signals before data transmission begins. The phase selector circuit can then simply select from these pre-prepared options based on observed setup failures, rather than requiring complex real-time phase adjustment during data transmission
3Manufacturing precision
If phase calibration is performed to eliminate setup failures, then data transfer accuracy improves, but the time required for calibration and setup increases
Solution Approach 1:
The patent applies partial action by generating only the necessary number of phase-shifted signals (e.g., 4 signals for 90° increments) rather than continuously adjusting phase across all possible values. This discrete approach achieves sufficient calibration accuracy without requiring extensive calibration time, as the phase selector can determine the optimal phase from a limited set of pre-generated options
Data Source
AI summary
An integrated circuit includes a first circuit block operating with a first clock signal and a second circuit block operating with a second clock signal. The first circuit block includes a clock phase generator that receives the first clock signal and outputs a plurality of phase signals. The first circuit block includes a phase selector that receives the phase signals and the second clock signal and selects one of the phase signals based on the second clock signal. The first circuit block transmits data to the second circuit block based on the selected phase signal.