Reception Clock Phase Shifting for Parallel Data Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing parallel data communication systems face challenges in maintaining synchronization between data signals and clock signals, particularly in high-speed data transmission, leading to desynchronization issues.
Innovation Solution
A method and circuit for generating a data reception clock signal that is out of phase with the transmitted clock signal, using an oscillating circuit, counter, and delay circuit to synchronize data signals by phase shifting the clock signal based on the protocol used (SDR, DDR, or QDR).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple communication channels are used to transmit data in parallel, then data transmission efficiency is improved, but synchronization between data signals and clock signals deteriorates
Solution Approach 1:
The patent changes the phase parameter of the clock signal by introducing a delay circuit that shifts the clock signal phase according to the data rate protocol (SDR, DDR, or QDR). This parameter adjustment enables proper synchronization of parallel data channels with the clock signal, resolving the synchronization deterioration issue while maintaining high data transmission efficiency.
2Reliability
If clock signal phase is adjusted to synchronize data signals, then data sampling stability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a delay circuit as an intermediary component between the clock signal source and the data sampling circuits. This intermediary element simplifies the overall system architecture by providing a centralized mechanism for phase adjustment, rather than requiring complex synchronization logic in each data channel, thus improving data sampling stability while minimizing the increase in device complexity.
3Manufacturing precision
If phase shifting is applied to the clock signal, then manufacturing variabilities are compensated, but energy consumption increases
Solution Approach 1:
The patent adjusts the phase parameter of the clock signal through a delay circuit to compensate for manufacturing variabilities in data transmission timing. This parameter change approach provides a flexible compensation mechanism that can adapt to different manufacturing tolerances without requiring additional energy-intensive components or complex calibration procedures, thus achieving variability compensation with minimal energy overhead.
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
The present description relates to a method for generating a first clock signal (S_Clk) from a second clock signal (Clk), the first and second clock signals having the same first period, and from a third periodic signal (Osc) having a second period equal to said first period divided by a number (K) greater than or equal to two, said method comprising the following successive steps: - counting a number (Cnt) of complete periods of said third signal carried out during a complete period of said second clock signal (Clk); and - generating said first clock signal (S_Clk) by phase shifting said second clock signal (Clk) by a delay (D) equal to said second period multiplied by another number between zero and said number (Cnt).